PCA9559PW,112 NXP Semiconductors, PCA9559PW,112 Datasheet - Page 3

• Manufacturer Part Number: PCA9559PW,112
• Description: IC I2C EEPROM 6BIT DIPSW 20TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9559PW,112

• Applications: PC's, PDA's
• Interface: I²C
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 20-TSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3400-5; 935265306112; PCA9559PW

Philips Semiconductors
FUNCTIONAL DESCRIPTION
When the MUX_SELECT signal is logic 0, the multiplexer will select
the data from the non-volatile register to drive on the MUX_OUT
pins. When the MUX_SELECT signal is logic 1, the multiplexer will
select the MUX_IN lines to drive on the MUX_OUT pins. The
MUX_SELECT signal is also used to latch the NON_MUXED_OUT
signal which outputs data from the non-volatile register. The
NON_MUXED_OUT signal latch is transparent when MUX_SELECT
is in a logic 0 state, and will latch data when MUX_SELECT is in a
logic 1 state. When the active-LOW OVERRIDE_N signal is set to
logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will
be driven to logic 0. This information is summarized in Table 1.
The Write Protect (WP) input is used to control the ability to write the
contents of the 6-bit non-volatile register. If the WP signal is logic 0,
the I
register. If the WP signal is logic 1, data will not be allowed to be
written into the non-volatile register.
The factory default for the contents of the non-volatile register are all
logic 0. These stored values can be read or written using the
I
The OVERRIDE_N, WP, MUX_IN, and MUX_SELECT signals have
internal pull-up resistors. See the DC and AC Characteristics for
hysteresis and signal spike suppression figures.
FUNCTION TABLE
NOTE:
1. NON_MUXED_OUT state will be the value present on the output
2003 Jun 27
2
OVERRIDE_N MUX_SELECT
C-bus (described in the next section).
5-bit multiplexed/1-bit latched 6-bit
I
at the time of the MUX_SELECT input transitioned from a logic 0
to a logic 1 state.
2
2
C-bus will be able to write the contents of the non-volatile
C EEPROM DIP switch
0
0
1
1
0
1
0
1
MUX_OUT
OUTPUTS
From non-
MUX_IN
MUX_IN
register
volatile
All 0’s
inputs
inputs
NON_MUXED
NON_MUXED_OUT
From non-volatile
From non-volatile
OUTPUT
Latched
register
register
All 0’s
_OUT
1
3
I
Communicating with this device is initiated by sending a valid
address on the I
fixed bits and two user-programmable bits followed by a 1-bit
read/write value which determines the direction of the data transfer.
Following the address and acknowledge bit are 8 data bits which,
depending on the read/write bit in the address, will read data from or
write data to the non-volatile register. Data will be written to the
register if the read/write bit is logic 0 and the WP input is logic 0.
Data will be read from the register if the bit is logic 1. The four
high-order bits are latched outputs, while the four low order bits are
multiplexed outputs (Figure 3).
NOTE:
1. To ensure data integrity, the non-volatile register must be
POWER-ON RESET (POR)
When power is applied to V
PCA9559 in a reset state until V
the reset condition is released and the PCA9559 volatile registers
and I
The MUX_OUT and NON_MUXED_OUT pin values depend on:
2
C INTERFACE
- the OVERRIDE # and MUX_SELECT logic levels
- the previously stored values in the EEPROM register/current
internally write protected when V
down or V
operating levels.
MSB
MUX_IN pin values as shown in the Function Table.
2
0
C/SMBus state machine will initialize to their default states.
MSB
1
CC
0
2
to the component is dropped below normal
C-bus. The address format (see FIgure 1) has 5
0
MUXED
Figure 2. I
NON-
DATA
Figure 3. I
0
FIXED
DATA E
CC
1
MUX
, an internal power-on reset holds the
2
1
C Address Byte
CC
2
C Data Byte
DATA D
HARDWARE
SELECTABLE
has reached V
MUX
CC
A1
to the I
A0
DATA C
MUX
R/W
2
LSB
C-bus is powered
PCA9559
DATA B
POR
MUX
. At that point,
Product data
DATA A
MUX
LSB