PCA9540BGD,125 NXP Semiconductors, PCA9540BGD,125 Datasheet - Page 4

• Manufacturer Part Number: PCA9540BGD,125
• Description: IC I2C MUX 2CH 8-XSON
• Manufacturer: NXP Semiconductors

Specifications of PCA9540BGD,125

• Package / Case: 8-XSON
• Applications: Translating Multiplexer
• Interface: I²C
• Voltage - Supply: 2.3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Product: Multiplexer
• Propagation Delay Time: 0.3 ns
• Mounting Style: SMD/SMT
• Power Dissipation: 400 mW
• Logical Function: I2C Multiplexer
• Configuration: 1 x 2:1
• Number Of Inputs: 2
• Number Of Outputs: 1
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4943-2; 935290165125

NXP Semiconductors
6. Functional description
PCA9540B_4
Product data sheet
6.2.1 Control register definition
6.1 Device addressing
6.2 Control register
Refer to
Following a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9540B is shown in
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9540B which will be stored in the Control register. If multiple bytes are
received by the PCA9540B, it will save the last byte received. This register can be written
and read via the I
A SCx/SDx downstream pair, or channel, is selected by the contents of the Control
register. This register is written after the PCA9540B has been addressed. The 2 LSBs of
the control byte are used to determine which channel is to be selected. When a channel is
selected, it will become active after a STOP condition has been placed on the I
This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made
active, so that no false conditions are generated at the time of connection.
Fig 5.
Fig 6.
Figure 1 “Block diagram of
Slave address
Control register
2
C-bus.
Rev. 04 — 3 September 2009
7
X
1
X
6
1
PCA9540B”.
X
5
slave address
1
enable bit
X
4
fixed
0
X
3
0
channel selection bits
B2
2
0
(read/write)
B1
002aae717
1
002aae716
0
Figure
B0
0
R/W
2-channel I
5.
PCA9540B
2
C-bus multiplexer
© NXP B.V. 2009. All rights reserved.
2
C-bus.
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