TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet

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... IDT  PCI/X-to-VME Bus Bridge User Reference Manual 80A3020_MA001_13 6024 Silver Creek Valley Road San Jose, California 95138 Telephone: (408) 284-8200 • FAX: (408) 284-3572 ©2009 Integrated Device Technology, Inc. ® Tsi148 TM  October 15, 2009 Printed in U.S.A. ...

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Integrated Device Technology, Inc. ("IDT") reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance. IDT does not assume responsibility for use of any circuitry described herein ...

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... Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.2 VMEbus Interface 1.2.1 2eVME Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.2.2 2eSST Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.2.3 VME Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.2.4 VME Master 1.2.5 Tsi148 as a VMEbus System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.3 PCI/X Interface 1.3.1 PCI/X Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.3.2 PCI/X Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.4 Linkage Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.5 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.5.1 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 1 ...

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... VME Master Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.3 VME Master Read-Modify Write (RMW) Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.4 VME Master Bandwidth Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.3.5 VMEbus Exception Handling 2.3.6 Utility Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.7 Tsi148 as a VMEbus System Controller PCI/X Interface 3.1 Overview of the PCI/X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.2 PCI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.2.1 PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.2.2 PCI Master ...

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... Signals and Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.1 Overview of Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.2 Signal Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.3 Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.4 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 8.4.1 PCI/X Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 8.4.2 VMEbus Signal Descriptions 157 8.4.3 Miscellaneous Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Contents 5 ...

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... LCSR Register Group Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 10.4.4 GCSR Register Group Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 10.4.5 CR/CSR Register Group Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 10.4.6 PCFS Register Group Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 10.4.7 Vendor ID/ Device ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 10.4.8 Command/Status Registers 214 10.4.9 Revision ID / Class Code Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

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... Error Diagnostic PCI/X Address Lower Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 10.4.43 Error Diagnostic PCI-X Attribute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 10.4.44 Error Diagnostic PCI-X Split Completion Message Register . . . . . . . . . . . . . . . . . . . 273 10.4.45 Error Diagnostic PCI/X Attributes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 10.4.46 Inbound Translation Starting Address Upper (0-7) Registers . . . . . . . . . . . . . . . . . . . 277 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Contents 7 ...

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... DMA Current Destination Address Upper (0-1) Registers . . . . . . . . . . . . . . . . . . . . . 337 10.4.81 DMA Current Destination Address Lower (0-1) Registers . . . . . . . . . . . . . . . . . . . . . 338 10.4.82 DMA Current Link Address Upper (0-1) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 10.4.83 DMA Current Link Address Lower (0-1) Registers 340 8 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

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... CR/CSR Bit Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 10.4.102 CR/CSR Bit Set Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 10.4.103 CR/CSR Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 A. Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 A.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 A.2 Tsi148 Connection Schematics 370 B. Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 B.1 Tsi148 PLL Filtering 381 B.2 Capacitance Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 B.3 Recommended Board Layout Guidelines ...

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... Contents 10 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

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... List of Figures Figure 1: Tsi148 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 2: Typical Application — Tsi148 In Single Board Computer Application Figure 3: Divisions of the CRG Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 4: CR/CSR Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 5: Slave Image Programmable Address Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 6: VMEbus to PCI/X Read Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 7: VMEbus to PCI/X Read Completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 8: VMEbus to PCI/X Write ...

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... Figure 43: Tsi148 Schematic (Page 43) - VME Control Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376 Figure 44: Tsi148 Schematic (Page 44) - VME Transceivers .377 Figure 45: Tsi148 Schematic (Page 45) - VME Transceivers .378 Figure 46: Tsi148 Schematic (Page 56) - PCI Bus 0.0 and 1.0 Pull-ups . . . . . . . . . . . . . . . . . . . . . . . . . .379 Figure 47: Tsi148 Schematic (Page 58) - PCI Bus 0.0 Configuration Header . . . . . . . . . . . . . . . . . . . . . .380 Figure 48: Recommended PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381 Figure 49: Tsi148 PBGA Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383 Figure 50: 456-Pin PBGA Package Diagram — ...

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... Table 20: I/O Power (3.3 V) — Sorted by Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Table 21: PCI/X Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 22: 3.3 V LVTTL DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 23: 5.0 V LVTTL DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 24: Common Receiver DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Table 25: LVTTL Driver DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 13 ...

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... Table 26: 1.8 V CMOS Driver DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 Table 27: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 Table 28: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Table 29: Tsi148 Total Power Dissipation (Core + IO .185 Table 30: Tsi148 Power Dissipation Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 Table 31: 456 EPBGA Package Thermal Performance for an 8 layer PCB . . . . . . . . . . . . . . . . . . . . . . .187 Table 32: 456 EPBGA Package Thermal Performance for a 4 layer PCB ...

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... Table 87: VMEbus Exception Address Upper Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Table 88: VMEbus Exception Address Lower Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Table 89: VMEbus Exception Attributes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Table 90: Error Diagnostic PCI/X Address Upper Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Table 91: Error Diagnostic PCI/X Address Lower Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 List of Tables 15 ...

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... Table 120: 64-bit Counter Upper Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 Table 121: 64-bit Counter Lower Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 Table 122: Broadcast Pulse Generator Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 Table 123: Broadcast Programmable Clock Timer Register .305 Table 124: VMEbus Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 16 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

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... Table 152: DMA Source Attribute (0-1) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Table 153: DSAT TYP Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Table 154: 2eSST Transfer Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Table 155: VMEbus Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Table 156: VMEbus Data Bus Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Table 157: VMEbus Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 List of Tables 17 ...

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... Table 172: Mail Box Registers (0- .363 Table 173: CR/CSR Bit Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364 Table 174: CR/CSR Bit Set Register .366 Table 175: CR/CSR Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368 Table 176: Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385 Table 177: Ordering Information .387 18 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

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... About this Document This chapter discusses general document information about the Tsi148 PCI/X-to-VME Bus Bridge User Manual. The following topics are described: • “Document Conventions” on page 19 • “Revision History” on page 22 • “Related Information” on page 24 Document Conventions This section explains the document conventions used in this manual. ...

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... The byte ordering convention is big-endian. Byte 0 represents the most significant bits of the word. This corresponds to the bit and byte ordering convention of the VMEbus. The VMEbus is not consistent in the bit and byte ordering. 20 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

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... Undefined values: For example, the device supports four channels depending on the setting of the PCI_Dx register. Terminology The following terms are used in this manual: • PCI/X: Refers to both the PCI and PCI-X bus. The PCI/X interface can be configured for either PCI or PCI-X operation. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 21 ...

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... The “Junction-to-Board and Junction-to-Case Characteristics” on page 187 was added 80A3020_MA001_10, Formal, April 2008 This revision of the Tsi148 PCI/X-to-VME Bus Bridge User Manual has the following change: • Clarifications have been made to • The TRST_ signal information was updated in ...

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... The mechanical outline drawing in the updated. 80A3020_MA001_07, Formal, March 2006 This revision of the Tsi148 PCI/X-to-VME Bus Bridge User Manual had the following changes: • The PERRM field in the Interrupt Map 2 Register had the function description corrected from DMA0 Interrupt Map to the PCI/X Bus Error Interrupt Map (see page 325) ...

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... This specification addresses the need for increased bandwidth of PCI Devices. PCI-X enables the design of systems and devices that can operate at speeds significantly higher than today's specification allows. For more information, see www.pcisig.com. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

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... Functional Overview This chapter describes the main features and functions of the Tsi148 are discussed: • “Overview of Tsi148” on page 26 • “Tsi148 Features” on page 27 • “Tsi148 Benefits” on page 28 • “Typical Applications” on page 28 • “VMEbus Interface” on page 30 • “PCI/X Interface” on page 35 • ...

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... Tsi148 eases design constraints of VME Single Board Computers (SBCs) by requiring less board real estate and power than the previous generation of VME-to-PCI/X bridge components. These capabilities make Tsi148 a key building block of the VME Renaissance and the development of next generation VME single board computers. Figure 1: Tsi148 Block Diagram 26 IEEE1149 ...

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... Interrupt and interrupt handling capability • Flexible register set; programmable from both PCI/X and VMEbus • IEEE 1149.1 Interface • 456 PBGA package, 1.0 mm ball pitch Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 1. Functional Overview > Overview of Tsi148 TM that describes an intense period of 27 ...

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... Reliable customer support with experience supporting the VME community for the past decade. 1.1.4 Typical Applications Tsi148 is intended for VME Single Board Computers and VME I/O peripheral cards that serve the following markets: • Telecommunications • Industrial automation • ...

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... Typical Application — Single Board Computers 1.1.4.1 The Tsi148 can be used on VME-based Single Board Computers (SBC) that employ PCI/X as their local bus and VME as the backplane bus, as shown in the accompanying diagram. These SBC cards support a variety of applications including telecommunications, datacommunications, medical, industrial automation, and military equipment. ...

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... Functional Overview > VMEbus Interface 1.2 VMEbus Interface The Tsi148 VMEbus Interface is compliant with the following standards: • American National Standard for VME64 (ANSI/VITA 1.0 - 1994 (R2002)) • American National Standard for VME64 Extensions (ANSI/VITA 1.1 - 1997) • Source Synchronous Transfer (2eSST) Standard For more information on the VME Interface refer to 1 ...

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... Section 1.4 on page master initiates a block read (BLT, MBLT, 2eVME, or 2eSST) transaction on the VMEbus. When the Tsi148 PCI/X Master receives a read request (after the VME Slave sends the read request requirements through the Linkage Module) , the PCI/X Master fills its read buffer by issuing burst requests to the PCI/X bus target ...

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... RMW cycles are not guaranteed indivisible on the PCI bus 1.2.4 VME Master The Tsi148 is VME Master when the VME Master is internally requested by the Linkage Module to service the PCI/X Target, DMA, or Interrupts. The internal Linkage Module arbitrates requests for each interface. Refer to on the Linkage Module. The Tsi148 ’ ...

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... Round-Robin-Select (RRS) • Single Level (SGL arbitration timer is included in the Tsi148 to prevent a bus lock-up from occurring when no requester assumes mastership of the bus after the arbiter has issued a grant. This timer can be enabled or disabled in the VMEbus Control and Status Register (see Section 10.4.34 on page 1 ...

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... Functional Overview > VMEbus Interface 1.2.5.3 SYSRESET Driver A SYSRESET driver is included in the Tsi148 to provide a global system reset. The SRSTO signal is asserted in the following cases: the LSRSTI_ pin is asserted, the SRESET bit is asserted in the VMEbus Control Status Register, or the PURSTI_ pin is asserted. The SRSTO signal is always asserted for at least 200 ms ...

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... Target has a 4 Kbyte read buffer, however, in conventional PCI mode a maximum of 512 bytes are used for storing prefetched data. When processing a read request the requesting PCI bus master is issued a retry from the Tsi148 PCI Target. The read request is then forwarded to the Linkage Module and then to the Tsi148 VME Master to be serviced. ...

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... PCI-X Target’s read data buffer to the original master . During write transactions, the PCI-X Target posts write data in its write buffer. The write buffer consists entry command queue and a 4 Kbyte data queue. Tsi148 issues the initiating PCI bus master immediate acknowledgement upon the write completing. Once the posted write completes on PCI-X, Tsi148 obtains the VMEbus and writes the data to the VMEbus resource independent of the initiating PCI-X master ...

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... Message signalled interrupts 1.4 Linkage Module The Tsi148 Linkage Module interconnects all the different modules that comprise Tsi148. The following modules are directly-connected to, and serviced by, the Linkage Module: • VMEbus: Master and Slave • PCI/X: Master and Target • DMA Controllers • ...

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... Functional Overview > Register Overview 1.5 Register Overview Tsi148’s 4 Kbyte register space is called the Combined Register Group (CRG). The CRG is divided into the following groups: • PCI Configuration Space registers (PFCS) • Local control and status registers (LCSR) • Global control and status registers (GCSR) • ...

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... The 512 Kbyte CR/CSR space, shown in the special A24 CR/CSR AM code (see The Base Address is defined by either Geographical Address Implementation or Auto Slot ID. Tsi148’s VME Slave can be configured at power-up to use one of the two methods (see Section 5.4 on page offset (located at offsets 0x418 – 0x420). ...

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... The principal mechanism for DMA transfers is the same for operations in either direction (PCI-to-VMEbus, or VMEbus-to-PCI), only the identity of the source and destination bus changes DMA transfer, the Tsi148 gains control of the source bus and reads data into the read buffer of the source master, then passes the data through the Linkage Module and into the DMA data buffer ...

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... The DMA buffer is emptied while being filled. 1.7 Interrupter and Interrupt Handler Tsi148 can be programmed to act as interrupter and an interrupt handler in a VME system interrupter, Tsi148 is capable of asserting interrupts on IRQ[7:1] interrupt handler, Tsi148 has several VMEbus Interrupt Acknowledge registers which, when read, generate an IACK cycle on the VMEbus (see ...

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... Functional Overview > JTAG 1.8 JTAG Tsi148 has a dedicated user-accessible test logic that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture; also referred to as JTAG (Joint Test Action Group). For more information on Tsi148’s JTAG capability refer to 42 Section 7 ...

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... VME Interface This chapter describes the main features and functions of the Tsi148 following topics are discussed: • “Overview of the VME Interface” on page 44 • “VME Slave” on page 44 • “VME Master” on page 55 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13  ...

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... Source Synchronous Transfer (2eSST) Standard The interface is separated into VME Slave and VME Master modules. The Tsi148 has been designed so that it can accept its own transaction on the VMEbus. If the Tsi148 VME Master initiates a transaction on the VMEbus, and the address falls within the inbound address window for the Tsi148 VME Slave, then the VME Slave accepts the cycle ...

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... The VMEbus is capable of many different transaction types, including one to four byte single beat transactions and burst transactions. These transactions must be mapped to corresponding transactions on the PCI/X bus. The Tsi148 supports all the different modes and protocols supported by the PCI/X bus and has numerous programmable options. Because of this flexibility there are many possible types of transactions between VME and PCI/X ...

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... Slave response control: VMEbus non-privileged, supervisory, program and data access cycles 46 Section 10.4.51 on page 282) and bits the ending 279) and bits the ending address in the Translation Section 10.4.49 on page Tsi148 PCI/X-to-VME Bus Bridge User Manual Section 10.4.46 on page 277) 280), are Section 10.4.52 80A3020_MA001_13 ...

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... If the VMEbus address is 16-bits, then the incoming VMEbus address bits are forced to zero and then bits the offset in the ITOFUx register and bits the offset in the ITOFLx register are added to VMEbus address bits Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 A63 ...

Page 48

... VME Interface > VME Slave 2.2.1.2 VME Slave Transactions The Tsi148 VMEbus Interface supports different transaction types, including one to four byte single beat transactions, and burst transactions. These transactions must be mapped to corresponding transactions on the destination bus. For more information on transaction mapping, refer to VME Slave Read Transaction VME Slave read operation depends on whether the transfer is a block or single cycle ...

Page 49

... Read Buffer Read Buffer VME Master 2. Tsi148 stores the command and address information, as well as byte count information ( 2eVME or 2eSST request) in the VME Slave’s read buffer command queue — Tsi148 supports one read request at a time Tsi148 PCI/X-to-VME Bus Bridge User Manual ...

Page 50

... After arbitration, the Linkage Module command and address information is passed to the PCI/X Master’s read buffer command queue. The PCI/X Master’s command queue is six entries deep. The 5. PCI/X Master 50 issues the read request to the PCI/X target Tsi148 PCI/X-to-VME Bus Bridge User Manual . 80A3020_MA001_13 ...

Page 51

... Linkage Module. 9. Once the VME Slave’s read buffer data queue is full (based on the virtual size programmed or byte count received), the read data is passed to the initiating VMEbus master. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 PCI/X Bus Write Buffer ...

Page 52

... During write transactions, the external master posts write data into the write buffer. All writes are posted and the write buffer stores the data necessary to complete the transfer and immediately acknowledges the transaction on the VMEbus. Tsi148 manages the completion of the posted write transaction. ...

Page 53

... Example VME Slave Write Transaction In this example VME-to-PCI/X write transaction, the data passes through Tsi148 through the VME Slave, to the Linkage Module, and ends at the PCI/X Master. The following list, and Figure 8, show the steps taken in the write transaction VMEbus master initiates a write to a PCI/X target. ...

Page 54

... The Tsi148 VME Slave responds to RMW cycles. The VME Slave does not complete VMEbus RMW cycles as indivisible cycles on the PCI/X bus. The PCI/X bus LOCK_ signal is not supported by the Tsi148 PCI/X Master and therefore the read and write cycles are divisible on the PCI/X bus. ...

Page 55

... A16, A24, A32, A64, and CR/CSR address phases. The address mode and type (supervisor and program) are also programmed through the Outbound Translation Attribute registers. The address and Address Modifier (AM) codes that are generated by the Tsi148 are functions of the mapping of the PCI/X memory space as defined above or through DMA programming (see Section 10 ...

Page 56

... A RMW cycle allows the VME Master to read from a VMEbus slave and then write to the same resource without relinquishing bus tenure between the two operations. RMW cycles can be generated by the Tsi148 VME Master. The VME Master generates RMW cycles on 8, 16, and 32-bit aligned transfers. For more information on the VME RMW registers, refer to Section 10 ...

Page 57

... VMEbus. The bits which do not compare are written to the VMEbus without modification. 6. The data read from the VMEbus is returned to the PCI/X Master. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 2. VME Interface > VME Master Figure 9) ...

Page 58

... VME Interface > VME Master Figure 9: Steps Used to Perform RMW Cycles on the VMEbus For information on how Tsi148 responds to RMW cycles as a VME Slave, refer to Section 2.2.1.3 on page 2.3.4 VME Master Bandwidth Control The VME Master has features to control VMEbus usage which can all be programmed in the ...

Page 59

... VME Master Release Conditions Tsi148 releases control of the VMEbus after it has been granted control as the VME Master when one of the following VMEbus release conditions are met: • The VMEbus is released when the time-on timer has reached its terminal count or the ...

Page 60

... The interrupt controller can be programmed to generate an interrupt when the exception registers are updated. 2.3.6 Utility Functions Tsi148 provides the following VMEbus utility functions: • VMEbus Location Monitor which allows one VMEbus board to broadcast an interrupt to multiple boards. The processor sends an interrupt by reading, or writing to, one of the VMEbus monitored addresses ...

Page 61

... Location monitor functionality allows one VMEbus board to broadcast an interrupt to multiple boards. All boards which are participating in the broadcast are programmed to monitor a set of VMEbus addresses. The Tsi148 location monitor is enabled in the Location Monitor (LMAT) Register by setting the Enable (EN) bit (see programmable in the Location Monitor Base Address Upper (LMBAU) register (see Section 10 ...

Page 62

... A semaphore register is only updated when bit 7 in the register is zero and a one is written to bit 7 of the register, or when a zero is written to bit 7. 62 Location Monitor Interrupt LM0 LM1 LM2 LM3 193) and Local Control and Status (LCSR) registers (see 193). Tsi148 PCI/X-to-VME Bus Bridge User Manual Table 2 shows the 80A3020_MA001_13 ...

Page 63

... Broadcast Interrupt and 64-bit Counter There are two Tsi148 VMEbus features which use the IRQ[1]_ or IRQ[2]_ signal lines in a device specific way: the Broadcast Interrupt and 64-bit Counter. When the IRQ[1]_ or IRQ[2]_ signal lines are used for the Broadcast Interrupt or 64-bit Counter features, they must not be used for VMEbus interrupt signals by any other boards ...

Page 64

... VME Interface > VME Master Broadcast Interrupt Although the Tsi148 IRQ[1] and IRQ[2] signals can be used as VMEbus interrupts (as defined by the American National Standard for VME64 Extensions), the Tsi148 can also use one of the IRQ[1] or IRQ[2] signals as a broadcast interrupt. The broadcast interrupt allows a board to send an interrupt to multiple boards ...

Page 65

... Round-Robin-Select (RRS) • Single Level (SGL arbitration timer is included in the Tsi148 to prevent a bus lock-up from occurring when no requester assumes mastership of the bus after the arbiter has issued a grant. This timer can be enabled or disabled in the VMEbus Control and Status Register (see Section 10.4.34 on page 2 ...

Page 66

... Global VMEbus Timer The Tsi148 has a VMEbus global timer that monitors VMEbus cycles and generates a BERR signal when there is no VMEbus slave response for the programmed time period. The global timer only monitors VMEbus cycles when the system controller function is enabled. The global timer is compatible with SCT, BLT, MBLT, 2eVME, and 2eSST transfers. The global time-out period can be programmed for 8, 16, 32, 64, 128, 256, 512, 1024, 2048  ...

Page 67

... PCI/X Interface This chapter describes the main features and functions of the Tsi148 are discussed: • “Overview of the PCI/X Interface” on page 68 • “PCI Mode” on page 68 • “PCI-X Mode” on page 82 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13  . The following topics ...

Page 68

... The PCI/X interface can be configured to operate in PCI mode or PCI-X mode. PCI-X mode is described in Section 3.3 on page 3.2 PCI Mode Tsi148 is compliant with the PCI Local Bus Specification (Revision 2.2). 3.2.1 PCI Target The PCI Target supports the PCI protocol, 32-bit and 64-bit data transfers, and 32-bit and 64-bit addresses. ...

Page 69

... PCI bus. The PCI address is compared with the address range of each target image, and if the address falls within the specified range, an offset is added to the incoming address to form the destination address. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Section 10.4.26 on page 239). 3. PCI/X Interface > ...

Page 70

... Configuration write • Memory read multiple • Dual address cycle — 64-bit address transactions • Memory read line • Memory write and invalidate 70 A16 A63 Translation Offset A16 Section 3.2.1.2 on page Tsi148 PCI/X-to-VME Bus Bridge User Manual A16 VME Address 69. 80A3020_MA001_13 ...

Page 71

... PCI bus master. This allows the PCI bus to be used by other PCI bus masters while Tsi148 completes the transfer. The PCI Target continues to retry the PCI bus master until the VMEbus transfer has been completed. If any other PCI bus masters try to use the PCI Target, they are retried ...

Page 72

... PCI MRPFD Command Bit X X Read 1 Read 0 Read Line X Read Multiple X Read Multiple X Read Multiple X Read Multiple X Tsi148 PCI/X-to-VME Bus Bridge User Manual PFS Linkage Bits Command X Single Beat X Single Beat X 32 bytes X 32 bytes 0 64 bytes 1 128 bytes 2 256 bytes 3 ...

Page 73

... Command Read Buffer VME Master 2. The Tsi148 PCI Target decodes the request and issues a retry to the PCI bus master 3. The PCI Target stores the command and address information in the PCI Target’s read buffer command queue — Tsi148 supports one delayed read request 4 ...

Page 74

... The VMEbus slave satisfies the read request and the data is stored in one of the two 4 Kbyte VME Master’s read buffer data queues. Having two buffers to store data allows the Tsi148 VME Master to do back-to-back reads on the VMEbus. 8. When the read request is satisfied and the data is queued in the VME Master’s data buffer, the VME Master makes a return request to the Linkage Module ...

Page 75

... Once the entire read request is queued in the PCI Target’s read buffer data queue the initial read request can be satisfied on PCI. — If the initiating PCI bus master makes a request for the data before the full request is satisfied in the read buffer data queue, Tsi148 retries the PCI bus master. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 76

... PCI bus from waiting for the potentially long VMEbus arbitration and transfer. This allows the PCI bus to be used by other PCI bus masters while Tsi148 completes the posted write transaction on the VMEbus. If the posted write buffer is full, the PCI Target retries the PCI bus master until there is space available in the write buffer ...

Page 77

... The PCI Target puts the corresponding data into its data queue 4. The PCI Target accepts write data until the write buffer fills or the transaction ends. 5. The PCI Target then sends a transaction request to the Linkage Module. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Figure 13, show the steps taken in the transaction ...

Page 78

... The burst ordering is non-linear • A burst read requires more data than was prefetched • A write burst fills the PCI Target write buffer The Tsi148 PCI Target never terminates a transaction with a Target-abort. 78 Section 10.4.36 on page 259) Tsi148 PCI/X-to-VME Bus Bridge User Manual ...

Page 79

... PCI Master Bandwidth Control The PCI bus latency timer can be used to control the PCI bus bandwidth used by Tsi148. The PCI Master requests the PCI bus when it has a transaction to complete (for example, when the PCI Master receives a command from the Linkage Module or when the master needs to complete a previously received command) ...

Page 80

... Error Diagnostic PCI Attributes (EDPAT) 3.2.3.1 PCI Master Exception Handling The error diagnostic registers are updated when Tsi148 is PCI Master and one of the following errors occurs: the master retry count is exceeded (programmed in the PCI Control / Status Register, see The Tsi148 interrupt controller can be programmed to generate an interrupt when the exception registers are updated ...

Page 81

... When the PCI Target detects a delayed transaction time-out the following steps are taken: • Discard Data • Log status information and update PCI bus exception registers • Optional step: generate interrupt If the PCI Target detects the assertion of the SERR_ signal, no action is taken. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 3. PCI/X Interface > PCI Mode 81 ...

Page 82

... PCI/X Interface > PCI-X Mode 3.3 PCI-X Mode Tsi148 is compliant with the PCI-X Addendum to PCI Local Bus Specification (Revision 1.0b). 3.3.1 PCI-X Target The PCI-X Target supports 32-bit and 64-bit data transfers and 32-bit and 64-bit addresses. The PCI-X Target supports configuration cycles to PCI-X configuration registers and memory space accesses ...

Page 83

... Writes — During a PCI-X bus write, the selected bytes on the PCI-X bus map directly to the destination bus. The Tsi148 does not write to bytes on the destination bus that are not selected on the PCI-X bus. — During a PCI-X bus memory write block, the number of bytes in the byte count, along with the starting address map directly to the destination bus. • ...

Page 84

... Memory write • Configuration read • Configuration write • Split completion • Dual address cycle • Memory read block • Memory write block 84 A16 A63 Translation Offset A16 Tsi148 PCI/X-to-VME Bus Bridge User Manual A16 VME Address Section 3.3.1.2 on 80A3020_MA001_13 ...

Page 85

... When the PCI-X Target receives a read request, the PCI-X Target saves the information required to complete the transfer and then issues a Split Response termination to the PCI-X bus master. This allows the PCI-X bus to be used by other PCI-X bus masters while Tsi148 completes the transfer. If the PCI-X Target receives a read request from a PCI-X bus master and the PCI-X Target read buffer command queue is full, the PCI-X Target retries the PCI-X bus master until there is space available in the read buffer ...

Page 86

... Data Command Read Buffer VME Master 2. The Tsi148 PCI-X Target decodes the request and issues a Split Response termination to the initiating PCI-X bus master 3. The PCI-X Target stores the command, address, and attribute information in the PCI-X Target’s read buffer command queue — ...

Page 87

... The VME Slave satisfies the read request and the data is stored in one of the two, 4 Kbyte VME Master read buffer data queues. Having two buffers to store data allows the Tsi148, through the VME Master back-to-back reads on the VMEbus. 8. Once the full byte count of the read request is satisfied and the data is queued in a VME Master’ ...

Page 88

... PCI-X Target read buffer data queue. 10. Once the entire read request is queued in the PCI-X Target’s read buffer data queue, Tsi148 issues a Split Completion through the PCI-X Master onto the PCI-X bus to the original, initiating PCI-X bus master. 11. The PCI-X Master transfers the data from the PCI-X Target’s read buffer data queue to the PCI-X bus master ...

Page 89

... PCI-X bus from waiting for the potentially long VMEbus arbitration and transfer. This allows the PCI-X bus to be used by other PCI-X bus masters while Tsi148 completes the posted write transaction on the VMEbus. If the posted write buffer is full, the PCI-X Target retries the PCI-X bus master until there is space available in the write buffer ...

Page 90

... PCI/X Interface > PCI-X Mode Example PCI-X Write Transaction In this example PCI-X-to-VME write transaction, the data passes through Tsi148 through the PCI-X Target, to the Linkage Module, and ends at the VME Master. The following list, and Figure 17, show the steps taken in the write transaction. ...

Page 91

... The PCI-X Target terminates a transaction with a disconnect on an address data boundary (ADB) in the following cases: • A transfer reaches the end of a target image • A burst write fills the write buffer Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 3. PCI/X Interface > PCI-X Mode 91 ...

Page 92

... PCI-X Master Bandwidth Control The PCI-X bus latency timer can be used to control the PCI-X bus bandwidth used by Tsi148. The PCI-X Master requests the PCI-X bus when it has a transaction to complete (for example, when the PCI-X Master receives a command from the Linkage Module or when it needs to complete a previously received command) ...

Page 93

... PCI-X Master Exception Handling The error diagnostic registers are updated when Tsi148 is PCI-X Master and one of the following errors occurs: the master retry count is exceeded, a split response time-out occurs, split completion error asserted Master-abort or Target-abort is received. The Tsi148 interrupt controller can be programmed to generate an interrupt, when the exception registers are updated ...

Page 94

... The split completion is discarded and the Split Completion Discarded (SCD) bit is set in the Error Diagnostic PCI Attribute register (see If the PCI-X Target detects the assertion of the SERR_ signal, no action is taken. 94 Section 10.4.43 on Section 10.4.43 on page 272). Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 95

... Because less time is required to complete transactions, applications that contain one or more DMA channels support faster read and write transfers than applications that support only host-assisted transactions. This chapter discusses the following topics about the Tsi148 DMA: • “Overview DMA Controller” on page 96 • ...

Page 96

... DMA Interface > Overview DMA Controller 4.1 Overview DMA Controller The Tsi148 has two independent, single channel DMA controllers that enable the transfer of large blocks of data without processor intervention. Each DMA controller is programmed by a set of registers that reside within the LCSR group (see The Combined Register Group (CRG) map decoder can be programmed to allow access to the control registers from the VMEbus ...

Page 97

... DMA transfer. In order to ensure all DMA data has been flushed from within the Tsi148, a local processor can initiate a read from VME memory (that is, a Tsi148 register in CR/CSR space, etc.) In Linked-list mode, the DMA controller executes a list of commands which are stored in system memory ...

Page 98

... Read Desc Desc Data Fetch Fetch Read Data Write Linked-List Mode, Various Transfers Bits 32 31 DSAU DDAU DSAT DNLAU DCNT 327). Transfer Data Desc Pattern Done Write Fetch Write 0 DSAL DDAL DDAT DNLAL DDBS Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 99

... Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 4. DMA Interface > Operating Modes 99 ...

Page 100

... For data pattern programming information refer to Section 10.4.89 on page 4.5.1 PCI/X-to-VME The Tsi148 DMA controllers support PCI/X-to-VME DMA transactions. Example DMA PCI/X-to-VME Transaction In this example, there is a DMA transaction between the PCI/X bus and VMEbus. The following list, and 1. Program the registers in the LCSR group. — ...

Page 101

... VME Master 2. Once these registers have been programmed, writing to the DGO bit in the DMA control register to initiates the DMA transfer. 3. The DMA controller issues a read request to the Linkage Module. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 PCI/X Bus Write Buffer Command ...

Page 102

... PCI/X Bus Write Buffer Command Data Write Buffer VMEbus Section 10.4.76 on page PCI/X Master Read Buffer Write Buffer Data DMA Controller Control Buffer Registers Read Buffer Write Buffer VME Slave 327). Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 103

... PCI/X Master attempts to fill the DMA buffer while the VME Master transfers data from the DMA buffer. 4.5.2 VME-to-PCI/X The Tsi148 DMA controllers support VME-to-PCI/X DMA transactions. 4.5.2.1 Example DMA VME-to-PCI/X Transaction In this example, there is a DMA transaction between the VMEbus and PCI/X bus. The following list, and 1 ...

Page 104

... The VME Master issues a read request to the VMEbus slave. 104 PCI/X Bus Write Buffer Command Write Buffer VMEbus PCI/X Master Read Buffer Write Buffer Data DMA Controller Control Buffer Registers Read Buffer Write Buffer VME Slave Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 105

... After arbitration, the read data is passed through the Linkage Module to the DMA controller’s data buffer. The data buffer is used to hold data that is transferred between the source and destination bus. 8. The DMA controller then issues a write request to the Linkage Module. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 PCI/X Bus Write Buffer ...

Page 106

... VME Master fills the DMA buffer while the PCI-X Master attempts to transfer data from the DMA buffer. 4.5.3 PCI/X-to-PCI/X The Tsi148 DMA controllers support PCI/X-to-PCI/X DMA transactions. 4.5.3.1 Example DMA PCI/X-to-PCI/X Transaction In this example, there is a DMA transaction between the PCI/X bus and PCI/X bus. The following list, and 1 ...

Page 107

... After arbitration, the Linkage Module passes the command, address information, and transfer size are passed to the PCI/X Master read buffer command queue. 5. The PCI/X Master issues a read request to the PCI/X target Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 PCI/X Bus Write Buffer ...

Page 108

... PCI/X Master write buffer command and data queues. 108 PCI/X Bus Write Buffer Command Write Buffer VMEbus PCI/X Master Read Buffer Write Buffer Data Data Command DMA Controller Control Buffer Registers Read Buffer Write Buffer VME Slave Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 109

... Master fills the DMA buffer to a certain point, after which the PCI/X Master empties the DMA buffer. 4.5.4 VME-to-VME The Tsi148 DMA controllers support VME-to-VME DMA transactions. 4.5.4.1 Example DMA VME-to-VME Transaction In this example, there is a DMA transaction between the VMEbus and VMEbus. The following list, and 1 ...

Page 110

... The VME Master issues a read request to the VMEbus slave. 110 PCI/X Bus Write Buffer Data Write Buffer VMEbus PCI/X Master Read Buffer Write Buffer DMA Controller Control Buffer Registers Read Buffer Write Buffer VME Slave Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 111

... The DMA controller issues a write request to the Linkage Module. 9. After arbitration, the command, information, address information, and write data is passed to a VME Master write buffer command and data queue. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 PCI/X Bus Write Buffer ...

Page 112

... Data Patterns The Tsi148’s DMA Controller can write data patterns to either VME or PCI/X space. The data patterns can be any size transfer, and there are no restrictions on the starting address. The is a starting data pattern is supplied by software. Software can also specify whether the pattern should be static or incrementing ...

Page 113

... PCI/X space is rounded off starting from the left side (Most Significant Bit) of the pattern, while a pattern written to VME space is rounded off starting from the right (or Least Significant Bit) side of the pattern. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 4. DMA Interface > Direction of Data Movement ...

Page 114

... DMA Interface > Direction of Data Movement 4.5.6 DMA Transaction Termination Tsi148 DMA activity can be terminated through either a transfer completion, commanded stop, commanded abort detected error abort. 4.5.6.1 Transfer Completion In most cases, a Direct mode transfer or a Linked-list mode transaction finishes without intervention or error. In Direct mode operation, the end of the transfer is considered completion ...

Page 115

... DMA activity. There are several methods available to control the bandwidth consumed by the DMA controller. The PCI/X bus latency timer and the VMEbus time-on timer can be used to control the VMEbus and PCI/X bus time allocated to the Tsi148. In addition the DMA controller has a programmable block size and back-off timer. ...

Page 116

... DMA Interface > Direction of Data Movement 116 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 117

... These include functions such as bus mode (PCI versus PCI/X) and data width size (32-bit versus 64-bit). This chapter discusses the following topics about Tsi148 Resets, Clocks, and Power-up Options: • ...

Page 118

... This section describes the reset capabilities, clocking requirements, and power-up options for the Tsi148 device. 5.2 Resets Tsi148 can be reset from both the VMEbus and the PCI/X bus. The device responds to both hardware and software reset events. reset structure. Figure 30: Tsi148 Reset Structure ...

Page 119

... JTAG Test Reset (TRST_): Provides asynchronous initialization of the TAP controller in the Tsi148. This signal must be tied to ground if JTAG is not used in the system. If JTAG is used in the system, the TRST_ input must be asserted low at the negation of the PURST_ input and then held high during boundary scan testing. — ...

Page 120

... SRSTO can be asserted either through hardware or software events. The hardware reset events are detailed in setting the SRESET bit in the VMEbus Control (VCTRL) register (see Section 10.4.34 on page If the SRESET bit is set, the Tsi148 asserts SRSTO output even not the system controller. The SRESET bit is self-clearing if SRSTI is connected to SRSTO through a transceiver. ...

Page 121

... VS bit is set, Tsi148 acquires VMEbus ownership. This prevents any other VMEbus masters from acquiring the VMEbus. Setting the VS bit also prevents Tsi148 from starting any VMEbus cycles. This ensures that the VMEbus idle state when the LRSTO_ signal is asserted. The LRESET bit can then be set. ...

Page 122

... Resets, Clocks, and Power-up Options > Resets 5.2.2 Reset Timing Figure 31 shows the power-up reset timing of Tsi148. The numbers in the figure correspond to the following values: • PLL_RST_ hold time (0ns) — PLL_RST_ can be released once the PCLK and power are stable • ...

Page 123

... Clocks Tsi148 clocks are derived from the PCI/X bus clock. The PCI/X bus clock frequency can be 33, 66, 100, or 133 MHz. PCLK operation below 33 MHz is not recommended. The PCI/X clock frequency and bus mode is configured on the rising edge of LRSTI_ (see Table ...

Page 124

... LRSTI_, then the chip is configured for 64-bit PCI/X. When the chip is used on a 32-bit PCI/X bus, REQ64_ should be pulled high with a weak pull-up resistor. When the Tsi148 is used on a 32-bit PCI/X bus, it drives CBE[7:4]_, AD[63:32], and PAR64 at all times. These signals may be left unconnected when the chip is used on a 32-bit PCI/X bus ...

Page 125

... LRSTI_ and the PCI/X bus is configured (as defined in the PCI-X Addendum to PCI Local Bus Specification (Revision 1.0b)). For more information, refer to page 123. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 5. Resets, Clocks, and Power-up Options > Power-up Options shows Tsi148’s PCI/X bus width configurations. Sample Reset Signal(s) LRSTI_ REQ64_ LRSTI_ ...

Page 126

... PURSTI_. During power-up reset Tsi148 negates the External Transceiver Enable (DBOE_) signal, which puts the VD[31:0], VA[31:1], LWORD transceivers into a high impedance state. External pull-ups or pull-downs placed between Tsi148 and the external transceivers bring these power-up option signals to their proper state while DBOE_ is negated. Table 7 shows the data signal and the functionality it enables through power-up configuration ...

Page 127

... VMEbus data bits. Table 9: CR/CSR Base Address Configuration VD[3:0] (All High) 00X0 00X1 0100 01X1 0110 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 5. Resets, Clocks, and Power-up Options > Power-up Options Table 8. 0 CR/CSR Disabled 1 Geographical Address ...

Page 128

... Auto Slot ID Operation Tsi148 has Auto Slot ID functionality which is described in the American National Standard for VME64. When the Auto Slot ID functionality is enabled in a system, after system reset each board in the system generates an interrupt on level IRQ2_. A level two interrupt handler module, called the Monarch, performs interrupt acknowledge cycles in response to each interrupt request ...

Page 129

... Section 10.4.34 on page When Auto Slot ID is used to assign the CR/CSR base address, the SFAILAI bit is set by the assertion of the SRSTI_ signal. The SFAILAI bit must be cleared in order for Tsi148’s System Fail Output (SFAILO) signal to be negated. SFAILO is automatically negated if the SFAILAI_AC power-up option is selected, otherwise SFAILO is negated when software clears the SFAILAI bit in the VCTRL register ...

Page 130

... Resets, Clocks, and Power-up Options > Power-up Options 5.4.2.4 System Fail Enable (SFAILEN) Configuration The Tsi148 System Failure Enable (SFAILEN) bit controls the assertion of the Tsi148 System Fail Output (SFAILO) signal. The only exception to this is when the Auto Slot ID method of assigning the CR/CSR base address is being implemented (as described in page 131) ...

Page 131

... System Controller (SCON) Tsi148 has VMEbus System Controller (SCON) functionality. The SCONEN_ and SCONDIS_ signals are used to control the SCON function. If the SCONEN_ signal is low and the SCONDIS_ signal is high at the rising edge of PUSRTI_, the SCON function is enabled. If the SCONEN_ signal is high and the SCONDIS_ signal is low at the rising edge of PURSTI_, the SCON function is disabled ...

Page 132

... Resets, Clocks, and Power-up Options > Power-up Options 132 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 133

... Interrupts generated by devices (for example, a printer) indicate an event has occurred and are called hardware interrupts. Interrupt events generated by software programs are called software interrupts. This chapter discusses the following topics about the Tsi148 interrupt features: • “Overview of the Interrupt Controller” on page 134 • ...

Page 134

... Interrupt Controller > Overview of the Interrupt Controller 6.1 Overview of the Interrupt Controller Tsi148 can be programmed to act as interrupter and an interrupt handler in a VME system interrupter, Tsi148 is capable of asserting interrupts on IRQ[7:1 interrupt handler, Tsi148 has seven VMEbus Interrupt Acknowledge registers which, when read, generate an IACK cycle on the VMEbus (see 6 ...

Page 135

... The edge sensitive interrupts also have a clear bit. These bits can be programmed in the Tsi148 Interrupt registers (see The Tsi148 expects the interrupt handling intelligence to exist on the local (PCI/X) bus. The Tsi148 does not have the ability to route local interrupt outputs (INTA_, INTB_, INTC_, INTD_) to VMEbus interrupt outputs (IRQ[7:1]) 6.4 ...

Page 136

... Interrupt Controller > VMEbus Interrupt Handler 136 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 137

... Board designers can develop a standard test for all 1149.1 compliant devices regardless of device manufacturer, package type, technology, or device speed. This chapter discusses the following topics about Tsi148’s JTAG features: • “Overview of JTAG” on page 138 • ...

Page 138

... JTAG Module > Overview of JTAG 7.1 Overview of JTAG Tsi148 has a dedicated user-accessible JTAG (Joint Test Action Group) module that is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. The JTAG logic includes a Test Access Port (TAP) consisting of five dedicated signals (TCK, TRST_, TMS, TDI, TDO), a TAP controller, instruction register, bypass register, other test data registers (for example, device identity register, etc ...

Page 139

... HIGHZ: This instruction is the same as BYPASS except that all the bidirect and 3-state outputs are 3-stated when this instruction is active. The boundary scan cell cannot be updated with a new value during this instruction. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 7. JTAG Module > Instructions ...

Page 140

... JTAG Module > Instructions 140 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 141

... Summary” on page 143 • “Detailed Signal Descriptions” on page 156 • “Pinout” on page 167 8.1 Overview of Signals The Tsi148 is a 456-pin device. The following sections explain Tsi148’s signal groups and characteristics. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 141 ...

Page 142

... SRSTI_ 1 SRSTO 1 1 SFAILI_ 1 1 SFAILO ACFAILI_ 1 1 AMOUT 1 1 DBOUT 1 10 DBOE_ 1 ADBOUT 1 ASOE 1 1 DSOE 1 1 BERROE 1 1 DTACKOE 1 1 RETRYOE 1 1 GA[4:0]_ 5 GAP_ 1 SCONEN_ 1 1 SCONDIS_ 1 1 SCON 32 1 SYSCLK Tsi148 PCI/X-to-VME Bus Bridge User Manual VMEbus 80A3020_MA001_13 ...

Page 143

... I/O cell, TTL compliant 5Vtlr TTL 3.3V I/O cell, TTL compliant, 5V tolerant 3.3V PCI/X PCI/PCI-X compliant 1.8V 1.8V I/O cell Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Type Input only Output only, Totem Pole Output only, Tri-state Output only, Open-drain ...

Page 144

... Table 14. I/O Function Type Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Tsi148 PCI/X-to-VME Bus Bridge User Manual . I/O I/O Level Drive Pin 3.3Vttl PCI-X AD19 3.3Vttl PCI-X AE18 3.3Vttl PCI-X AF19 3.3Vttl PCI-X AD18 3 ...

Page 145

... AD34 PCI Address/Data Bus [34] AD35 PCI Address/Data Bus [35] AD36 PCI Address/Data Bus [36] AD37 PCI Address/Data Bus [37] AD38 PCI Address/Data Bus [38] AD39 PCI Address/Data Bus [39] Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 I/O Function Type Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect ...

Page 146

... Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Tsi148 PCI/X-to-VME Bus Bridge User Manual I/O I/O Level Drive Pin 3.3Vttl PCI-X T2 3.3Vttl PCI-X T3 3.3Vttl PCI-X R2 3.3Vttl PCI-X R3 3.3Vttl PCI ...

Page 147

... PCI Data Parity Error SERR_ M66EN PCI Frequency Capability Select PCLK INTA_ INTB_ INTC_ INTD_ Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Function PCI Cycle Frame PCI Initiator Ready PCI Target Ready PCI Stop PCI Device Select PCI Bus Request PCI bus Grant ...

Page 148

... Bidirect 3.3Vttl 35ohm Bidirect 3.3Vttl 35ohm Bidirect 3.3Vttl 35ohm Bidirect 3.3Vttl 35ohm Bidirect 3.3Vttl 35ohm Bidirect 3.3Vttl 35ohm Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Pin W25 W23 Y26 W24 Y24 K24 L25 K26 L23 L24 M25 N23 M24 M23 N25 ...

Page 149

... VD8 VMEbus Data Bus [8] VD9 VMEbus Data Bus [9] VD10 VMEbus Data Bus [10] VD11 VMEbus Data Bus [11] VD12 VMEbus Data Bus [12] VD13 VMEbus Data Bus [13] Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 I/O Function Type Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect Bidirect ...

Page 150

... Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Pin C11 B12 D13 C12 D12 B13 A12 A13 C14 C13 A14 A15 B14 C15 D15 ...

Page 151

... BG1IN_ VMEbus Bus Grant 1 In BG2IN_ VMEbus Bus Grant 2 In BG3IN_ VMEbus Bus Grant 3 In BG0INOUT_ VMEbus Bus Grant 0 In/Out Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Function VMEbus Retry In VMEbus Retry Out 8. Signals and Pins > Signal Summary I/O I/O I/O ...

Page 152

... Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Tsi148 PCI/X-to-VME Bus Bridge User Manual I/O I/O Level Drive Pin 5Vtlrnt 35ohm A19 5Vtlrnt 35ohm C19 5Vtlrnt 35ohm D19 5Vtlrnt 35ohm A18 ...

Page 153

... VMEbus Data Strobe OE DTACKOE VMEbus Data Acknowledge OE BERROE VMEbus Bus Error OE RETRYOE SCONEN_ System Controller Enable SCONDIS_ System Controller Disable SCON Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Function VMEbus Retry OE System Controller 8. Signals and Pins > Signal Summary I/O I/O I/O Type Level ...

Page 154

... Output 1.8V 65ohm Input Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Pin AE22 AB25 AD4 AC3 B5 AB23 AE26 D5 C10 D10 ...

Page 155

... Table 14: Pin List Signal PLL_VSS PLL Analog Ground VDD18 VDD33 VSS Spares Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Function 1.8V Digital Supply 3.3V Digital Supply Digital Ground Unused pins 8. Signals and Pins > Signal Summary I/O I/O I/O Type Level Drive ...

Page 156

... Local Bus Specification (Revision 2.2) and the PCI-X Addendum to PCI Local Bus Specification (Revision 1.0b). For detailed descriptions of the operations of the signals, please refer to the specifications. 156 (Table 17 on page 168) are compliant with the PCI Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 157

... VMEbus Signal Descriptions The Tsi148 VME Interface is designed to be connected to the VMEbus through external buffers. Refer to the American National Standard for VME64, American National Standard for VME64 Extensions, and Source Synchronous Transfer (2eSST) Standard documents for a complete description of the VMEbus. ...

Page 158

... Tsi148 when it is the VME Master. Low I The WRITE_ signal is monitored by the VME Slave. O The WRITE_ signal is driven by Tsi148 when it is the VME Master. Low I The ASI_ signal is monitored by the VVME Master and VME Slave. Buffer Requirements This signal is connected to the VMEbus through an external bidirectional buffer ...

Page 159

... Signals and Pins > Detailed Signal Descriptions Active I/O Description Low O The ASO_ signal is driven by Tsi148 when it is the VME Master. Low I VMEbus data strobe 0 is monitored by Tsi148’s VME Slave. Low O VMEbus data strobe 0 is driven by Tsi148 during VME Master cycles. ...

Page 160

... VMEbus. These signals may be connected to the VMEbus BG[3:0]IN_ signals through external tri-state drivers. When external drivers are used, SCON is the enable signal. These signals are 5 volt tolerant and may be connected directly to the VMEbus. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 161

... Input IACKOUT_ Interrupt Acknowledge Output IRQ[7:1]I_ Interrupt Input IRQ[7:1]O Interrupt Output Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 8. Signals and Pins > Detailed Signal Descriptions Active I/O Description Low I The VMEbus bus busy signal is monitored by Tsi148’s VMEbus requester and arbiter. High ...

Page 162

... This signal is connected to the VMEbus through an external tri-state buffer. Since these signals are either grounded or open on the backplane, they can be connected directly to Tsi148. Since this signal is either grounded or open on the backplane, it can be connected directly to Tsi148. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 163

... DTACKOE Data Transfer Acknowledge Output Enable BERROE Bus Error Output Enable RETRYOE Retry Output Enable Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 8. Signals and Pins > Detailed Signal Descriptions Active I/O Description High O This signal is used to control the direction of the external buffers on the AM, IACK_ and WRITE_ signals ...

Page 164

... When SCONEN_ and SCONDIS_ signals are negated, the auto SCON function is enabled. Active I/O Low I/O When this signal is asserted, the SFAILO signal is asserted if the SYSFAIL inhibit bit is not set. Buffer Requirements Description Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 165

... These pins are the PCI bus interrupt outputs. High I When Tsi148 is configured in 32-bit PCI mode and this signal is low, the 64-bit extension signals are driven. When Tsi148 is configured in 32-bit PCI mode and this signal is high, the 64-bit extension signals are tri-stated. ...

Page 166

... These pins form the ground connections for all of the input macros, output macros, and core logic. I The +1.8V pin provides clean power to the internal Analog Phase Locked Loop. I This input provides clean ground to the internal Analog Phase Locked Loop. Description Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 167

... Pinout Tsi148’s pinout is illustrated in the following sections to locate pin assignments on the Tsi148: • Table 17 on page 168 • Table 18 on page 175 • Table 19 on page 178 • Table 20 on page 179 Figure 34: Pinout — Bottom View Tsi148 PCI/X-to-VME Bus Bridge User Manual ...

Page 168

... Signals and Pins > Pinout 8.5.1 Sorted by Pin Assignment The following table lists Tsi148’s pinout in numerical order according to pin assignment. Use this table along with Table 17: Pinout — Sorted by Pin Assignment Pin Assignment A03 A04 A05 A07 A08 A09 A10 A12 ...

Page 169

... C17 C18 C19 C20 C21 C22 C23 C25 C26 D01 D02 D03 D05 D06 D07 D08 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 8. Signals and Pins > Pinout Signal Name BG1IN_ BG3OUT_ BR0O BR2O BR3I_ BERROE AMOUT TDI SCONDIS_ PLL_TUNE8 PLL_OUTA PLL_TUNE5 ...

Page 170

... VD16 VD29 VD28 BBSYO BG0INOUT_ BG2OUT_ BG3INOUT_ BR0I_ BR3O DBOUT DTACKO_ DS0O_ DS1I_ INTB_ TMS SCONEN_ DTACKI_ SYSCLK DS0I_ IACKOUT_ TDO INTA_ DS1O_ ASO_ ASOE AD62 INTC_ INTD_ ASI_ RETRYOE IACKIN_ IACK_ AD59 AD63 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 171

... L24 L25 M01 M02 M03 M23 M24 M25 M26 N01 N02 N03 N23 N24 N25 N26 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 8. Signals and Pins > Pinout Signal Name AD61 RETRYO_ AM0 RETRYI_ AM3 AD57 AD60 AD58 AM1 AM4 AM2 LWORD_ ...

Page 172

... VA13 VA17 VA15 AD45 AD42 AD43 VA19 VA18 VA21 VA16 AD40 AD41 VA23 VA22 VA25 NO CONNECT AD37 AD39 VA28 VA26 VA29 VA24 AD38 AD34 AD36 ACFAILI_ VA30 NO CONNECT VA27 AD35 PAR64 AD33 LRSTI_ PURSTI_ Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 173

... AC02 AC03 AC24 AC25 AC26 AD01 AD02 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 8. Signals and Pins > Pinout Signal Name LRSTO_ VA31 AD32 CBE6_ CBE7_ SFAILO BDFAIL_ SRSTO LSRSTI_ ACK64_ CBE4_ IRQ2O ...

Page 174

... AD6 AD3 AD0 GA2_ GAP_ IRQ5O IRQ5I_ IRQ4I_ IRQ3O FRAME_ STOP_ IDSEL CBE2_ PAR AD30 AD27 NO CONNECT AD22 AD19 AD17 AD11 AD9 AD7 AD4 AD1 GA3_ GA1_ IRQ7I_ CE0_TEST IRQ6I_ NO CONNECT TM_OUT DEVSEL_ TRDY_ Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 175

... AF18 AF19 AF20 AF22 AF23 AF24 8.5.1.1 Ground Pins The following table lists Tsi148’s ground pins in numerical order according to pin assignment. Use this table along with assignments. Table 18: VSS (Ground) — Sorted by Pin Assignment Pin Assignment A01 A02 A06 A11 ...

Page 176

... VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 177

... AB13 AB18 AC04 AC23 AD03 AD24 AE01 AE02 AE25 AF01 AF06 AF11 AF16 AF21 AF25 AF26 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 8. Signals and Pins > Pinout Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ...

Page 178

... Signals and Pins > Pinout 8.5.1.2 Power Pins The following tables lists Tsi148’s core and I/O power pins in numerical order according to pin assignment. Use this table along with names or pin assignments. Table 19: Core Power (1.8 V) — Sorted by Pin Assignment Pin Assignment ...

Page 179

... Table 20 shows Tsi148’s I/O power pins in numerical order according to pin assignment. Use this table along with Table 20: I/O Power (3.3 V) — Sorted by Pin Assignment Pin Assignment E04 E06 E07 E08 E13 E19 E20 E21 F04 F05 F22 G04 G05 G22 ...

Page 180

... VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 181

... Absolute maximum ratings, if available, define the maximum operating conditions such as supply voltage, power, and operating temperature. This chapter discusses the following topics about Tsi148’s electrical characteristics: • “Operating Conditions” on page 184 • ...

Page 182

... Tsi148 ’s electrical characteristics are defined by PCI/X electrical characteristics and non-PCI/X electrical characteristics. 9.1.1 PCI/X Electrical Characteristics The Tsi148's PCI/X interface is electrically compatible with the 3.3V signaling interface as defined by the PCI-X Addendum to PCI-X Addendum to PCI Local Bus Specification (Revision 1.0b) and the PCI Local Bus Specification (Revision 2.2). Table 21 specifies DC characteristics of all Tsi148’ ...

Page 183

... Non-PCI Electrical Characteristics The following tables detail the DC characteristics of all non-PCI/X Tsi148 signal pins. Table 22: 3.3 V LVTTL DC Electrical Characteristics Symbol Parameter V Input low voltage IL V Input high voltage IH Table 23: 5.0 V LVTTL DC Electrical Characteristics Symbol Parameter V Input low voltage IL V Input high voltage ...

Page 184

... LVTTL Input Voltage IN V 5V-Tolerant Input Voltage Input Current IN T Storage Temperature Range STG 184 Condition I = -6.1 mA (65 ohm output 6.0 mA (65 ohm output) OL Tsi148 PCI/X-to-VME Bus Bridge User Manual Min Max Units 1.2 V 0.45 V Min Max Unit -0.3 2.0 V -0.3 3 ...

Page 185

... Power Supply Sequencing The Tsi148 uses the 1.8V supply to power its core logic and the 3.3V supply to power its I/O buffers. If the 3.3V is supplied before the 1.8V, the Tsi148 I/O buffers are in an undefined state, and possibly driving, until the core 1.8V is applied recommended to supply the 1 ...

Page 186

... These results are based on the Tsi148 being routed layer PCB. It should be noted that the thermal simulations for a JEDEC standard 4 layer PCB with a worst case power dissipation of 1.84W, the Tsi148 does not have sufficient thermal performance to meet the industrial grade requirements. If the worst case die power dissipation is less than or equal to 1 ...

Page 187

... Table 32: 456 EPBGA Package Thermal Performance for a 4 layer PCB Air Flow (m/ 9.4.2 Junction-to-Board and Junction-to-Case Characteristics Table 33 shows the simulated Thetajb and Theta jc thermal characteristics of the Tsi148 package. Table 33: Thermal Characteristics of Tsi148 Interface Theta jb (junction-to-board) Theta jc (junction-to-case) Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 9. Electrical Characteristics > ...

Page 188

... Electrical Characteristics > Electrostatic Discharge (ESD) 9.5 Electrostatic Discharge (ESD) The Tsi148 is a Charge Device Model test (CDM) Class II device as classified in the JEDEC JESD22-C101-A Specification. classifications for the Tsi148 device. Table 34: Tsi148 ESD Classification ESD Test Human Body Model (HBM) Machine Model ...

Page 189

... Use ionization systems to help dissipate residual charge built up on any material that is static generating and is in close proximity to the Tsi148 • Use a field strength meter to check items that come into contact with the Tsi148. The field strength meter tool is useful in confirming safe surfaces and those that contain residual charges needing neutralizing ionizers. ...

Page 190

... Electrical Characteristics > Electrostatic Discharge (ESD) 190 Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 191

... Registers This appendix describes the Tsi148’s registers. The following topics are discussed: • “Overview of Registers” on page 192 • “Register Groupings” on page 192 • “Register Endian Mapping” on page 195 • “Register Map” on page 197 Tsi148 PCI/X-to-VME Bus Bridge User Manual ...

Page 192

... PCI/X Configuration Space registers (PCFS), the Local Control and Status Registers (LCSR), the VMEbus Global Control and Status Registers (GCSR) and the VMEbus Configuration ROM / Control and Status Registers (CR/CSR). Registers can be accessed by the Tsi148 PCI/X Target or the VME Slave through the internal Linkage Module. 10.2 Register Groupings Tsi148 register space is separated into different groups within Tsi148 ...

Page 193

... Control and Status Registers (CSR) The CSR register group is a sub-set of the CR/CSR section of the CR/CSR registers defined in the American National Standard for VME64 Extensions. Tsi148 implementation of these standard registers include: the CR/CSR Bit Clear, CR/CSR Bit Set, and CR/CSR Base Address Registers ...

Page 194

... Tsi148’s VME Slave can be configured at power-up to use one of the two methods (see Section 5.4 on page AM code, the Tsi148 initiates an access on the PCI/X bus when the enable bit in the CR/CSR Attribute Register is set (located at offset 0x420). The address generated on the PCI/X bus is determined by the values in the CR/CSR Offset registers (located at offsets 0x418 and 0x41C) ...

Page 195

... Figure 37: Big to Little Endian Data Swap When viewed from the VMEbus, the LCSR, GCSR and CR/CSR registers appear as presented in the programming section. When viewed from the VMEbus, the PCFS registers appear swapped. Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 ...

Page 196

... VMEbus data in the correct order. When a processor operating in little endian mode is used, the VMEbus data appears swapped. 196 Value on Value on PCI/X bus Processor bus ABCD DCBA DCBA ABCD DCBA ABCD DCBA ABCD Tsi148 PCI/X-to-VME Bus Bridge User Manual Value on VMEbus DCBA ABCD ABCD ABCD 80A3020_MA001_13 ...

Page 197

... Register Map The register map shows all the Tsi148 register groupings in the Combined Register Group (CRG). The CRG requires 4 Kbytes of address space. The address space can be mapped into PCI/X address space or VMEbus address space. Refer to information on the CRG and all the group that comprise the Tsi148 registers. ...

Page 198

... Memory Base Address Upper (MBARU) Reserved Reserved Reserved Reserved for more Vendor ID (VENI) Command (CMMD) Revision ID (REVI) Cache Line Size (CLSZ) Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Offset PCFS/ CRG 0x00/ 0x000 0x04/ 0x004 0x08/ 0x008 0x0C/ 0x00C 0x10/ 0x010 ...

Page 199

... Table 36: PCFS Register Group Function 31 PCI/X Header Configuration PCI-X Capabilities Reserved Tsi148 PCI/X-to-VME Bus Bridge User Manual 80A3020_MA001_13 Bits Reserved Subsystem ID (SUBI) Reserved Reserved Reserved Maximum Minimum Grant Latency (MNGN) (MXLA) PCI-X Capabilities (PCIXCAP) PCI-X Status (PCIXSTAT) Reserved Reserved Reserved 10. Registers > Register Map ...

Page 200

... Outbound Translation Ending Address Upper 0 (OTEAU0) Outbound Translation Ending Address Lower 0 (OTEAL0) Outbound Translation Offset Upper 0 (OTOFU0) Outbound Translation Offset Lower 0 (OTOFL0) Outbound Translation 2eSST Broadcast Select 0 (OTBS0) Outbound Translation Attribute 0 (OTAT0) Tsi148 PCI/X-to-VME Bus Bridge User Manual Offset CRG 0x100 ...