TSI148-133CL IDT, Integrated Device Technology Inc, TSI148-133CL Datasheet - Page 327

• Manufacturer Part Number: TSI148-133CL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133CL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1906

DMA Control (0-1) Re
Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
Bits
2:0
3
Reserved
ABT (Abort): Writing a one to this field aborts a DMA transaction. An abort is considered an
unrecoverable operation to a DMA transaction, meaning that an aborted transaction may not
be restarted. When issuing an abort, both the PCI/X and/or VMEbus masters are immediately
stopped and all FIFO contents are invalidated. Once the abort has taken affect, the DSTA
BSY bit is cleared and the DON and ERR bits is set. Reading this field always returns a zero.
PAU (Pause): Writing a one to this field pauses a DMA transaction. This bit is only
applicable to Linked-List-Mode transactions. When pausing a DMA transaction, the DMA
controller stops at the completion of the current linked-list transfer. If the pause took affect
before the completion of a transaction, then the DTSA. The PAU field is set once the DMA
Controller reaches the paused state. A paused transaction may be restarted by writing a one to
the DGO field. Reading this field always returns a zero.
DGO (DMA Go): Writing a one to this field starts a DMA transaction. Reading this field
always returns a zero.
MOD (Mode): This bit establishes the type of DMA transaction to be performed. If set, a
Direct-Mode transaction is performed. A Direct-Mode transaction performs one transfer
according to the contents of the DSAD, DSAT, DDAD, DDAT, and DCNT registers. If
cleared, a Linked-List-Mode transaction is performed. A Linked-List-Mode transaction
performs multiple transfers that are driven by a list of descriptors stored in PCI/X memory
space. A Linked-List-Mode transaction obtains the first descriptor from the starting address
placed within the DNLA register.
VFAR (VME Flush on Aborted Read): If this bit is set and a VMEbus cycle is terminated
with an exception, any data remaining in the FIFO is transferred to the destination. If this bit
is cleared and a VMEbus cycle is terminated with an exception, any data remaining in the
DMA FIFO is discarded.
Name
PBOT
g
ister
Abort (ABT) has authority over Pause (PAU). If a commanded pause is followed
by an commanded abort, then the DMA controller honors the commanded abort.
N/A
PCI/X Back-off Timer
Function
PCFS
Space
Type
R/W
R
10. Registers > Register Map
Reset
P/S/L
N/A
By
Reset
Value
0x00
0x00
327