LMH0070SQE/NOPB National Semiconductor, LMH0070SQE/NOPB Datasheet - Page 8

• Manufacturer Part Number: LMH0070SQE/NOPB
• Description: IC SERIALIZER/CABLE DVR 48-LLP
• Manufacturer: National Semiconductor

Specifications of LMH0070SQE/NOPB

• Applications: Displays
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 3.135 V ~ 3.465 V
• Package / Case: 48-LLP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH0070SQE; LMH0070SQE; LMH0070SQETR

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Functional Description
DEVICE OPERATION
The SER is used in digital video signal origination equipment.
It is intended to be operated in conjunction with an FPGA host
which preprocesses data for it, and then provides this data
over the five bit wide data path. Provided the host has properly
formatted the data for the SER, the output of the device will
be compliant with DVB-ASI, SMPTE 259M-C, SMPTE 292M
or SMPTE 424M depending upon the output mode selected.
National Semiconductor offers IP in source code format to
perform the appropriate formatting of the data, as well as
evaluation platforms to assist in the development of target
applications. For more information please contact your local
National Semiconductor Sales Office/Distributor.
POWER SUPPLIES
The SER has several power supply pins, at 2.5V as well as
3.3V. It is important that these pins all be connected, and
properly bypassed. Bypassing should consist of parallel
4.7μF and 0.1μF capacitors as a minimum, with a 0.1μF ca-
pacitor on each power pin. The device has a large contact in
the center of the bottom of the package. This contact must be
connected to the system GND as it is the major ground con-
nection for the device. A 22 μF capacitor is required on the
V
Discrete bypassing is ineffective above 30 MHz to 50 MHz in
power plane-based distribution systems. Above this frequen-
cy range, the intrinsic capacitance of the power-ground sys-
tem can be used to provide additional RF bypassing. To make
the best use of this, make certain that there are PCB layers
dedicated to the Power supplies and to GND, and that they
are placed next to each other to provide a distributed capac-
itance between power and GND.
The SER will work best when powered from linear regulators.
The output of linear regulators is generally cleaner with less
noise than switching regulators. Output filtering and power
system frequency compensation are generally simpler and
more effective with linear regulators. Low dropout linear reg-
ulators are available which can usually operate from lower
input voltages such as logic power supplies, thereby reducing
regulator power dissipation. Cascading of low dropout regu-
lators should not be done since this places the entire supply
current load of both load systems on the first regulator in the
cascade and increases its loading and thermal output.
POWER UP
The 3.3V power supply should be brought up before the 2.5V
supply. The timing of the supply sequencing is not important.
The device has a power on reset sequence which takes place
once both power supplies are brought up. This sequence will
reset all register contents to their default values, and will place
the PLLs into link acquisition mode, attempting to lock on the
TXCLK input.
RESET
There are three ways in which the device may be reset. There
is an automatic reset which happens on power-up; there is a
reset pin, which when brought low will reset the device, with
normal operation resuming when the pin is driven high again.
The third way to reset the device is a soft reset, implemented
via a write to the reset register. This reset will put all of the
register values back to their default values, except it will not
affect the address register value if the SMBus default address
has been changed.
DDPLL
pin which is connected to the 3.3V rail.
8
LVDS INPUTS
The SER has LVDS inputs that conform with the ANSI/TIA/
EIA-644–A Standard. These inputs have an internal 100 Ω
resistor across the inputs which allows for the closing of a
current loop interface from the LVDS driver in the host. It is
recommended that the PCB trace between the FPGA and the
transmitter be less than 25cm. Longer PCB traces may intro-
duce signal degradation as well as channel skew which could
cause serialization errors. This connection between the host
and the SER should be over a controlled impedance trans-
mission line with an impedance which matches the termina-
tion resistor – usually 100 Ω. Setup and hold times are
specified in the LVDS Switching Characteristics table, how-
ever there is the ability to change these by use of the CLK
delay adjustment available via the SMBus, and writing to reg-
ister 0x30'h.
LVDS DATA ORDER
When serializing the data, the data bit latched in on TX0 is
output first, followed by TX1, TX2, TX3 and then TX4. If start-
ing with a 10 bit word, T0..T9, with T0 being the LSB, and it
is desired that this be serialized such that the LSB is sent out
first, then the least significant 5 bit word would be provided to
the serializer first, followed by the most significant word, and
the resulting serialized output would have the LSB being sent
first, and the 10 bit MSB (T9) would be transmitted last. If it is
desired to reverse the serialization order, such that the bit
presented on TX4 is output first, this mode of operation may
be selected via register 0x2E'h.
LOOP FILTER
The SER has an internal PLL which is used to generate the
serialization clock from the parallel clock input. The loop filter
for this PLL is external, and for optimum results in Serial Dig-
ital Interface applications, a capacitor and a resistor in series
should be connected between pins 26 and 27. Recommend-
ed value for the capacitor is 0.1 μF. Recommended value for
the resistor is 500 Ω.
PLL FILTER / BYPASS
The SER has an external filter capacitor for the PLL. The rec-
ommended value for this capacitor is 22 μF with a connection
to the 3.3V rail.
DVB_ASI MODE
The SER has a special mode for DVB-ASI. In this mode, the
input signal on TX4± is treated as a data valid bit, if high, then
the four bit nibbles from TX0-TX3 are taken to form an 8 bit
word, which is then converted to a 10 bit code via an internal
8b10b encoder and this 10 bit word is serialized and driven
on the output. The nibble taken in on the rising edge of the
clock is the most significant nibble and the nibble taken in on
the falling edge is the least significant nibble. If TX4± is low,
then the input on TX0-TX3 are ignored and the 10b idle char-
acter is inserted in the output stream. The Idle character can
be reprogrammed to be any 10 bit code desired via registers
0x11'h and 0x12'h.
SDI OUTPUT INTERFACING
The serial outputs provide low-skew complimentary or differ-
ential signals. The output buffer is a current mode design, with
a high impedance output. To drive a 75Ω transmission line
connect a 75Ω resistor from each of the output pins to 2.5V.
This resistor has two functions – it converts the current output
to a voltage, which is used to drive the cable, and it acts as
the back termination resistor for the transmission line. The
resistor should be placed as close to the output pin as is