PCA9518D,112 NXP Semiconductors, PCA9518D,112 Datasheet
PCA9518D,112
Specifications of PCA9518D,112
935272404112
PCA9518D
Available stocks
Related parts for PCA9518D,112
PCA9518D,112 Summary of contents
Page 1
PCA9518 Expandable 5-channel I Rev. 05 — 2 December 2008 1. General description The PCA9518 is a BiCMOS integrated circuit intended for application in I SMBus systems. While retaining all the operating modes and features of the I extension of ...
Page 2
... NXP Semiconductors 2. Features I Expandable 5 channel, bidirectional buffer C-bus and SMBus compatible I Active HIGH individual repeater enable inputs I Open-drain input/outputs I Lock-up free operation I Supports arbitration and clock stretching across the repeater I Accommodates Standard-mode and Fast-mode I I Powered-off high-impedance I I Operating supply voltage range of 3 3.6 V ...
Page 3
... NXP Semiconductors 4. Block diagram EXPSCL1 EXPSCL2 SCL0 SCL1 SCL2 EXPSDA1 EXPSDA2 SDA0 SDA1 SDA2 EN1 EN2 Fig 1. Block diagram of PCA9518 A more detailed view of Fig 2. The output pull-down voltage of each internal buffer is set for approximately 0.5 V, while the input threshold of each internal buffer is set about 0.07 V lower, when the output is internally driven LOW ...
Page 4
... NXP Semiconductors 5. Pinning information 5.1 Pinning EXPSCL1 EXPSCL2 SCL0 SDA0 SCL1 SDA1 EN1 SCL2 SDA2 GND Fig 3. 5.2 Pin description Table 2. Symbol EXPSCL1 EXPSCL2 SCL0 SDA0 SCL1 SDA1 EN1 SCL2 SDA2 GND EN2 SCL3 SDA3 EN3 SCL4 SDA4 EN4 EXPSDA1 EXPSDA2 ...
Page 5
... NXP Semiconductors 6. Functional description The PCA9518 BiCMOS integrated circuit is a five-way hub repeater, which enables 2 I C-bus and similar bus systems to be expanded in increments of five with only one repeater delay and no functional degradation of system performance. The PCA9518 BiCMOS integrated circuit contains five multi-directional, open-drain buffers specifi ...
Page 6
... NXP Semiconductors Standard-mode devices and multiple masters are possible. Please see application note AN255, I resistors. 7. Application design-in information A typical application is shown 3 100 kHz unless slave 3, slave 4 and slave 5 are isolated from the bus. Then the master bus and slave 1, slave 2 and slave 6 can run at 400 kHz. ...
Page 7
... NXP Semiconductors or, when the bus 0 SDA reaches 0.7V EXPSDA2 and EXPSDA1 are HIGH the rest of the SDA lines are allowed to rise. The same description applies for the EXPSCL1, EXPSCL2, and SCL pins SDA SDA1 SCL SCL1 SUBSYSTEM 5 100 kHz 3.3 V SDA ...
Page 8
... NXP Semiconductors V SCL of master Bus 0 SDA of master t PHL1 EXPSDA1 t PHL2 EXPSDA2 expansion bus EXPSCL1 EXPSCL2 SCL of slave Bus 1 SDA of slave t PHL Bus n with n > 1 Fig 6. Bus waveforms It is important to note that any arbitration or clock stretching events on Bus 1 require that the V OL Section 9 “ ...
Page 9
... NXP Semiconductors 8. Limiting values Table 3. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol I2C-bus tot T stg T amb [1] Voltages with respect to pin GND. PCA9518_5 Product data sheet Limiting values Parameter Conditions supply voltage C-bus voltage SCL or SDA input current ...
Page 10
... NXP Semiconductors 9. Static characteristics Table 4. Static characteristics 3.6 V; GND = Symbol Parameter Supplies V supply voltage CC I HIGH-level supply current CCH I LOW-level supply current CCL I contention LOW-level supply CCLc current Input SCL; input/output SDA V HIGH-level input voltage IH V LOW-level input voltage IL V contention LOW-level input voltage SCL, SDA ...
Page 11
... NXP Semiconductors 10. Dynamic characteristics Table 5. Dynamic characteristics Symbol Parameter t HIGH to LOW propagation delay PHL t LOW to HIGH propagation delay PLH t HIGH to LOW propagation delay 1 PHL1 t LOW to HIGH propagation delay 1 PLH1 t LOW to HIGH propagation delay 2 PLH2 t HIGH to LOW output transition time THL t LOW to HIGH output transition time ...
Page 12
... NXP Semiconductors 11. Test information Fig 8. PCA9518_5 Product data sheet PULSE GENERATOR load resistor; 1.1 k for I C-bus, and 500 load capacitance includes jig and probe capacitance; 100 pF for I L EXPxxxn termination resistance should be equal Test circuit for open-drain outputs Rev. 05 — 2 December 2008 ...
Page 13
... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
Page 14
... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 15
... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
Page 16
... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
Page 17
... NXP Semiconductors Fig 11. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 8. Acronym CDM BiCMOS DUT ESD HBM I C-bus MM RC SMBus PCA9518_5 Product data sheet ...
Page 18
... Release date PCA9518_5 20081202 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 6.1 • Figure 5 “Typical application: multiple expandable 5-channel I below drawing. • ...
Page 19
... NXP Semiconductors Table 9. Revision history …continued Document ID Release date • Modifications: Table 5 “Dynamic (continued) – symbol/parameter “t “t PHL column) – symbol/parameter “t “t PLH column) – symbol/parameter “t to “t PHL1 Conditions column) – symbol/parameter “t to “t PLH1 Conditions column) – ...
Page 20
... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
Page 21
... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Enable 6.2 Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 6.3 I C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Application design-in information . . . . . . . . . . 6 8 Limiting values Static characteristics Dynamic characteristics ...