Z1601720ASG1868 Zilog, Z1601720ASG1868 Datasheet - Page 89

• Manufacturer Part Number: Z1601720ASG1868
• Description: IC PCMCIA INTERFACE 100-VQFP
• Manufacturer: Zilog

Specifications of Z1601720ASG1868

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Each count equals PC_MCLK_IN /2.
Programming Internal Registers
NOTES:
Bit Placement
Bit 3
Bit 5-4
Bit 7-6
7
0
0
0
0
0
0
0
0
6
0
0
0
0
1
1
1
1
5
0
0
1
1
0
0
1
1
Table 58.
The ATA_HIOR/HIOW strobe width is three cycles minimum
(PC_MCLK_IN /2), plus IOCHRDY time (if any), plus width count
programmed in bits 5, 4 (Table 59).
Table 59.
Bit Name
EN_MAP_IO_MEM
DUECE_WIDTH
DUECE_ACCESS_DLY
4
0
1
0
1
0
1
0
1
Bits
Delay
0
0
0
0
1
1
1
1
Bus Control Register: Address 2Fh (Continued)
Strobe Width and Access Delay
Width
0
1
2
3
0
1
2
3
Z86017/Z16017 PCMCIA Interface Solution
Description
When this bit is set, all memory accesses are mapped to
ATA_HIOR and ATA_HIOW. When it is cleared, all
memory accesses are mapped to ATA_MRD and
ATA_MWR.
These bits set the ATA_HIOR/HIOW strobe width and are
clocked by PC_MCLK_IN /2. At Power-On Reset, they
default to 00.
These bits set the ATA_HIOR/HIOW access delay and are
clocked by PC_MCLK_IN /2. At Power-On Reset, they
default to 00.
7
1
1
1
1
1
1
1
1
6
0
0
0
0
1
1
1
1
5
0
0
1
1
0
0
1
1
1
Product Specification
4
0
1
0
1
0
1
0
1
Bits
Delay
2
2
2
2
3
3
3
3
PS012002-1201
Width
0
1
2
3
0
1
2
3
75