DS33X42+ Maxim Integrated Products, DS33X42+ Datasheet - Page 281

• Manufacturer Part Number: DS33X42+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X42+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
0018h:
Default
0019h:
Default
001Ah:
Default
001Bh:
Default
Bits 16-31: Pause Time (PT[15:0]) - Contains the 16-bit value to be used in the time field in transmitted PAUSE
control frames.
Bit 4: Pause Low Threshold (PLT) - Set to 1 for 1000Mbps operation. Should equal 0 for 10/100Mbps operation.
Recommended settings for PT and PLT.
Application
10Mbps
100Mbps
1Gbps (MPL <2049)
1Gbps (MPL > 2048)
Notes: “slots” are defined by the IEEE as the amount of time that it takes to transmit 64 bytes for 10/100Mbps and 512
bytes for 1000Mbps. Only the 10/100Mbps applications are applicable for the Port 2 MAC.
Bit 3: Unicast Pause Frame Detect (UP) - When set to 1, the MAC will detect Pause control frames with the
device’s unicast address, in addition to detecting Pause control frames with a multicast address. When equal to
zero, the MAC will only detect Pause control frames with the unique multicast address as specified in the 802.3x
standard.
Bit 2: Receive Flow Control Enable (RFE) - When set to 1, the MAC will receive Pause control frames and
disable the transmitter for the specified pause time. When this bit is equal to zero, the device will not respond to
Pause control frames.
Bit 1: Transmit Flow Control Enable (TFE) - When operating in Full-Duplex mode, if this bit is set, the MAC will
transmit Pause control frames as needed. When equal to zero, the MAC will not transmit Pause control frames.
Bit 0: Flow Control Busy (FCB) - This bit is equal to 1 when the transmission of a Pause control frame is in
progress. If the user writes a “1” to this bit, the device will transmit one Pause control frame.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Reserved
Reserved
PT[15]
Bit 31
Bit 23
Bit 15
PT[7]
Bit 7
0
0
0
0
Reserved
Reserve
PT[14]
Bit 30
Bit 22
Bit 14
Bit 6
PT[6]
d
0
0
0
0
Value
176 slots
176 slots
44 slots
72 slots
SU.MACFCR
MAC Flow Control Register
0018h (indirect)
Reserved
Reserved
PT[0:15]
PT[13]
Bit 5
Bit 29
Bit 21
Bit 13
PT[5]
0
0
0
0
Time
9.01ms
90.1μs
901μs
147μs
Reserved
PT[12]
Bit 28
Bit 20
Bit 12
PT[4]
Bit 4
PLT
0
0
0
0
Value
0
0
1
1
PLT
Reserved
PT[11]
Bit 27
Bit 19
Bit 11
PT[3]
Bit 3
Time
UP
7.37ms
73.7μs
737μs
131μs
0
0
0
0
Reserved
Retransmit Rate
1 Pause Every
PT[10]
Bit 26
Bit 18
Bit 10
PT[2]
Bit 2
RFE
0
0
0
0
1.64ms
16.4μs
16.4μs
164μs
Reserved
Bit 25
Bit 17
PT[9]
PT[1]
Bit 9
Bit 1
TFE
0
0
0
0
Reserved
281 of 375
Bit 24
Bit 16
PT[8]
PT[0]
Bit 0
FCB
Bit 8
0
0
0
0