DS33X42+ Maxim Integrated Products, DS33X42+ Datasheet - Page 80

• Manufacturer Part Number: DS33X42+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X42+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
8.19 Ethernet MAC
Indirect addressing is required to access the Ethernet MAC registers. Writing to the Ethernet MAC registers
requires address and data information to be loaded into multiple registers, and the write operation initiated through
a control bit. Reading from the MAC registers requires address information to be loaded into two registers, the read
operation initiated through a control bit. After the read operation completes, data is read from four registers.
Algorithm for Indirect MAC Write Operation:
1) Read SU.MAC1RWC.MCS and verify that a read/write access is not in progress.
2) Write the address for the access into the SU.MAC1AWL and SU.MAC1AWH registers.
3) Write the data to be written into the SU.MAC1WD0-3 registers.
4) Write SU.MAC1RWC = 0x01.
5) Poll SU.MAC1RWC.MCS until the bit is clear, indicating that the write operation has completed.
Algorithm for Indirect MAC Read Operation:
1) Read SU.MAC1RWC.MCS and verify that a read/write access is not in progress.
2) Write the address for the access into the SU.MAC1RADH and SU.MAC1RADL registers.
3) Write SU.MAC1RWC = 0x03.
4) Poll SU.MAC1RWC.MCS until the bit is clear, indicating that the read operation has completed.
5) Read the data from SU.MAC1RD0-SU.MAC1RD3.
Note that only one operation can be initiated (read or write) at one time. Data cannot be written or read from the
MAC registers until the SU.MAC1RWC.MCS bit has been cleared by the device. The MAC Registers are listed in
the following table.
Rev: 063008
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