DS33X42+ Maxim Integrated Products, DS33X42+ Datasheet - Page 41

• Manufacturer Part Number: DS33X42+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X42+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.5
EXAMPLE DEVICE INITIALIZATION SEQUENCE:
STEP 1: Reset the device
STEP 2: Configure Serial Ports, TX VCAT, RX VCAT, Encapsulator, Decapsulator
STEP 3: Enable transmit serial, transmit VCAT, Encapsulator, Receive LAN
STEP 4: Enable transmit and receive MAC1 (SU.MACCR.TE, SU.MACCR.RE)
STEP 5: Enable transmit and receive MAC2 (SU.MACCR.TE, SU.MACCR.RE)
STEP 6: Enable receive VCAT, Decapsulator, Transmit LAN
STEP 7: Enable Interrupts
8.6
The set of Global Registers begin at address location 000h. The global registers include Global resets, global
interrupt status, interrupt masking, clock configuration, and the Device ID registers. See the Global Register
Definitions in Table 10-2.
8.7
The device contains a common set of global registers. The Serial (Line) Interfaces each have a set of registers for
configuration and control, denoted in this document with the “LI.” prefix. The Ethernet (Subscriber) Interfaces each
have a set of registers for configuration and control, denoted in this document with the “SU.” prefix.
8.8
Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global
Interrupt Status register GL.ISR to initially determine the source of the interrupt. The host can then read the higher-
level status registers to further identify the source of the interrupt(s). All global status bits (GL.ISR) and
intermediate status bits (AR.BMIS, VCAT.RISR) are real-time bits that will clear once all appropriate interrupts
have been serviced and cleared. The interrupts from any source can be blocked at a global level by the writing a
zero in appropriate location in the global interrupt enable register GL.IER. Some portions of the device use interrupt
mask registers. Placing a “1” in the associated bit location associated with an interrupt condition prevents that
condition from causing a device interrupt. Some portions of the device use interrupt enable registers. Placing a “1”
in the associated bit location associated with an interrupt condition allows that condition to cause a device interrupt.
Latched Status bits that have been enabled or are un-masked are allowed to pass their interrupt conditions to the
Global Interrupt Status Registers. The Interrupt enable registers allow individual Latched Status conditions to
generate an interrupt, but when set to zero, they do not prevent the Latched Status bits from being set. Therefore,
when servicing interrupts, the user should AND the Latched Status with the associated Interrupt Enable Register in
order to exclude bits for which the user wished to prevent interrupt service. The user should NAND the Latched
Status bits with the associated Interrupt Mask Register. Latched Status Registers clear once read as described in
Section 8.1.2. This architecture allows the application host to periodically poll the latched status bits for non-
interrupt conditions, while using only one set of registers.
Note that the inactive state of the interrupt output pin is configurable. The GL.CR2.INTM bit controls the inactive
state of the interrupt pin, allowing selection of high-impedance or active
The interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source. The
latched status bits for the interrupting entity must be read to clear the interrupt. Note that reading one latched status
bit will reset all bits in that register. During a reset condition, interrupts cannot be generated.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Initialization and Configuration
Global Resources
Per-Port Resources
Device Interrupts
driver.
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