MT18HTF25672AZ-80EH1 Micron Technology Inc, MT18HTF25672AZ-80EH1 Datasheet - Page 14

• Manufacturer Part Number: MT18HTF25672AZ-80EH1
• Description: MODULE DDR2 SDRAM 2GB 240UDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT18HTF25672AZ-80EH1

• Memory Type: DDR2 SDRAM
• Memory Size: 2GB
• Speed: 800MT/s
• Features: -
• Package / Case: 240-UDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 13: DDR2 I
Values shown for MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-
ponent data sheet
PDF: 09005aef83c6d17f
htf18c128_256_512x72az.fm - Rev. C 12/10 EN
Parameter
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
Precharge quiet standby current: All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
Active power-down current: All device banks open;
t
stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
(I
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
CK (I
RP (I
OUT
RP =
DD
),
= 0mA; BL = 4, CL = CL (I
DD
DD
t
t
RP (I
RC =
DD
OUT
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
); CKE is LOW; Other control and address bus inputs are
),
DD
= 0mA; BL = 4, CL = CL (I
t
t
RP =
RC (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus
DD
t
RP (I
),
DD
t
RRD =
DD
Notes:
Specifications and Conditions – 4GB (Die Revision C) (Continued)
DD
); CKE is HIGH, S# is HIGH between valid commands;
t
CK =
), AL = 0;
t
RRD (I
DD
t
1. Value calculated as one module rank in this operating condition; all other module ranks
2. Value calculated reflects all module ranks in this operating condition.
), AL = 0;
CK (I
in I
DD
DD
1GB, 2GB, 4GB (x72, ECC, DR) 240-Pin DDR2 SDRAM UDIMM
t
DD
CK =
DD2P
),
), AL =
); REFRESH command at every
t
RCD =
t
CK =
t
(CKE LOW) mode.
CK (I
t
RCD (I
t
t
DD
RCD (I
CK (I
),
t
CK =
t
DD
RAS =
DD
t
DD
CK =
) - 1 ×
),
t
); CKE is HIGH, S# is
CK =
t
t
CK (I
RAS =
t
t
CK =
t
RAS MAX (I
t
CK (I
CK =
14
t
CK (I
DD
t
),
t
DD
RAS MAX (I
CK (I
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
t
DD
CK (I
); CKE is
RAS =
);
t
DD
RFC (I
t
DD
DD
CK =
Micron Technology, Inc. reserves the right to change products or specifications without notice.
); CKE is
t
),
); CKE
RAS
t
DD
RP =
DD
t
CK
)
),
Symbol
I
I
I
I
I
I
I
DD4W
DD2Q
DD2N
DD3N
I
I
I
DD2P
DD3P
DD4R
DD5
DD6
DD7
2
2
1
2
2
1
2
2
2
1
-1GA
TBD
TBD
TBD
TBD
TBD
TBD
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TBD
TBD
TBD
© 2009 Micron Technology, Inc. All rights reserved.
IDD Specifications
-80E/
-800
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-667
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Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA