MT36HTF1G72PZ-80EC1 Micron Technology Inc, MT36HTF1G72PZ-80EC1 Datasheet - Page 10

• Manufacturer Part Number: MT36HTF1G72PZ-80EC1
• Description: MODULE DDR2 SDRAM 8GB 240RDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT36HTF1G72PZ-80EC1

• Memory Type: DDR2 SDRAM
• Memory Size: 8GB
• Speed: 800MT/s
• Features: -
• Package / Case: 240-RDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I
Table 10: DDR2 I
Values shown for MT47H128M4 DDR2 SDRAM only and are computed from values specified in the 512Mb (128 Meg x 4)
component data sheet
PDF: 09005aef83d65c27
htf36c256_512_1gx72pz.pdf - Rev. D 10/10 EN
Parameter
Operating one bank active-precharge current:
t
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL (I
(I
switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
Active power-down current: All device banks open;
(I
Data bus inputs are floating
Active standby current: All device banks open;
(I
trol and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
=
are switching; Data bus inputs are switching
Burst refresh current:
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
DD
RAS =
OUT
DD
DD
DD
t
RP (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
); CKE is LOW; Other control and address bus inputs are stable;
),
DD
= 0mA; BL = 4, CL = CL (I
Specifications
t
RP =
), AL = 0;
DD
t
RAS MIN (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
t
RP (I
t
DD
DD
CK =
DD
); CKE is HIGH, S# is HIGH between valid commands; Other con-
), AL = 0;
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
t
CK (I
Specifications and Conditions – 2GB (Die Revision F)
t
CK =
DD
t
DD
CK =
),
t
CK (I
), AL = 0;
t
RC =
t
CK (I
DD
DD4W
2Gb, 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
t
); REFRESH command at every
RC (I
DD
t
CK =
),
DD
t
RAS =
),
t
t
CK (I
RAS =
t
CK =
t
t
RAS MAX (I
CK =
DD
t
CK =
t
),
RAS MIN (I
t
CK =
t
t
CK (I
RAS =
t
CK (I
t
OUT
CK =
t
t
CK (I
CK =
10
t
DD
CK
= 0mA; BL = 4, CL =
DD
DD
t
),
t
DD
RAS MAX (I
CK (I
),
t
DD
),
t
CK (I
); CKE is HIGH, S#
RAS =
t
RC =
t
),
RP =
t
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
RFC (I
DD
t
RCD =
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
); CKE is
t
t
); CKE is
t
RC (I
RAS MAX
RP (I
DD
DD
t
) inter-
RCD
DD
),
DD
t
),
RP
);
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
1
1
2
2
2
2
1
2
2
2
1
© 2009 Micron Technology, Inc. All rights reserved.
I
-80E/
DD
1926
2196
1800
1980
1440
2520
3636
3186
4266
-800
252
432
252
Specifications
1746
2016
1620
1800
1260
2340
3186
3366
3366
-667
252
432
252
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA