UJA1069TW24/3V0:51 NXP Semiconductors, UJA1069TW24/3V0:51 Datasheet - Page 25

• Manufacturer Part Number: UJA1069TW24/3V0:51
• Description: IC LIN FAIL-SAFE 24-HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/3V0:51

• Applications: Automotive
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 3V
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280016512; UJA1069TW24/3V0; UJA1069TW24/3V0

NXP Semiconductors
Table 3.
UJA1069_3
Product data sheet
Register
address bits
(A1, A0)
00
01
10
11
Register overview
6.12.1 SPI register mapping
6.12.2 Register overview
6.12.3 Mode register
Operating
mode
all modes
Normal mode;
Standby mode;
Flash mode
Start-up mode;
Restart mode
Normal mode;
Standby mode
Start-up mode;
Restart mode;
Flash mode
Normal mode;
Standby mode
Start-up mode;
Restart mode;
Flash mode
Any control bit which can be set by software is readable by the application. This allows
software debugging as well as control algorithms to be implemented.
Watchdog serving and mode setting is performed within the same access cycle; this only
allows an SBC mode change whilst serving the watchdog.
Each register carries 12 data bits; the other 4 bits are used for register selection and
read/write definition.
The SPI interface gives access to all SBC registers; see
A0) of the message header define the register address, the third bit is the read register
select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO)
allows ‘read only’ access to one of the feedback registers. Which of the SBC registers can
be accessed also depends on the SBC operating mode.
In the Mode register the watchdog is defined and re-triggered, and the SBC operating
mode is selected. The Mode register also contains the global enable output bit (EN) and
the Software Development Mode (SDM) control bit. During system operation cyclic access
to the Mode register is required to serve the watchdog. This register can be written to in all
modes.
At system start-up the Mode register must be written to within t
RSTN (HIGH-level on pin RSTN). Any write access is checked for proper watchdog and
system mode coding. If an illegal code is detected, access is ignored by the SBC and a
system reset is forced in accordance with the state diagram of the system controller; see
Figure
4.
Write access (RO = 0)
Mode register
Interrupt Enable register
Special Mode register
System Configuration
register
General Purpose register 0
Physical Layer Control
register
General Purpose register 1
Rev. 03 — 10 September 2007
Read access (RO = 0 or RO = 1)
Read Register Select
(RRS) bit = 0
System Status register
Interrupt Enable Feedback
register
Interrupt Enable Feedback
register
System Configuration
Feedback register
System Configuration
Feedback register
Physical Layer Control
Feedback register
Physical Layer Control
Feedback register
Table
LIN fail-safe system basis chip
3. The first two bits (A1 and
Read Register Select
(RRS) bit = 1
System Diagnosis register
Interrupt register
Special Mode Feedback
register
General Purpose Feedback
register 0
General Purpose Feedback
register 0
General Purpose Feedback
register 1
General Purpose Feedback
register 1
WD(init)
from releasing
UJA1069
© NXP B.V. 2007. All rights reserved.
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