EA-QSB-012 Embedded Artists, EA-QSB-012 Datasheet
EA-QSB-012
Specifications of EA-QSB-012
Related parts for EA-QSB-012
EA-QSB-012 Summary of contents
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... Rev. 3 — 10 August 2010 1. General description The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex- next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. ...
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... May be run from the system oscillator or the internal RC oscillator. For USB (LPC1342/43), a second, dedicated PLL is provided. Code Read Protection (CRP) with different security levels. Unique device serial number for identification. Available as 48-pin LQFP package and 33-pin HVQFN package. 3. Applications ...
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... HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2 HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 × 7 × 0.85 mm ...
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NXP Semiconductors 5. Block diagram HIGH-SPEED GPIO ports GPIO PIO0/1/2/3 RXD TXD (2) DTR, DSR , CTS, (2) (2) DCD , RI , RTS CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP0 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 CT16B1_MAT[1:0] ...
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NXP Semiconductors 6. Pinning information 6.1 Pinning PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 Fig 2. LPC1343 LQFP48 package LPC1311_13_42_43 Product data sheet 1 PIO2_6 XTALIN 6 LPC1343FBD48 7 XTALOUT PIO2_7 ...
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... NXP Semiconductors PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 Fig 3. LPC1342/43 HVQFN33 package LPC1311_13_42_43 Product data sheet terminal 1 index area PIO2_0/DTR 1 2 RESET/PIO0_0 3 XTALIN 4 LPC1342FHN33 XTALOUT 5 LPC1343FHN33 Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2010 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller ...
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NXP Semiconductors PIO2_6 PIO2_0/DTR RESET/PIO0_0 PIO0_1/CLKOUT/CT32B0_MAT2 V XTALIN XTALOUT V PIO1_8/CT16B1_CAP0 PIO0_2/SSEL/CT16B0_CAP0 PIO2_7 PIO2_8 Fig 4. LPC1313 LQFP48 package LPC1311_13_42_43 Product data sheet LPC1313FBD48 All information ...
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... NXP Semiconductors PIO0_1/CLKOUT/CT32B0_MAT2 PIO0_2/SSEL/CT16B0_CAP0 Fig 5. LPC1311_13_42_43 Product data sheet terminal 1 index area 1 PIO2_0/DTR RESET/PIO0_0 2 3 XTALIN 4 LPC1311FHN33 LPC1313FHN33 5 XTALOUT PIO1_8/CT16B1_CAP0 7 8 Transparent top view LPC1311/13 HVQFN33 package All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 August 2010 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller ...
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... C Fast-mode Plus is selected in the I/O configuration register. I PIO0_6 — General purpose digital input/output pin USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor under software control. Used with the SoftConnect USB feature (LPC1343 only). I/O - SCK — Serial clock for SSP. I PIO0_7 — ...
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NXP Semiconductors Table 3. LPC1313/43 LQFP48 pin description table Symbol Pin Start logic input [3] SWCLK/PIO0_10/ 29 yes SCK/CT16B0_MAT2 [5] R/PIO0_11/ 32 yes AD0/CT32B0_MAT3 [5] R/PIO1_0/ 33 yes AD1/CT32B1_CAP0 [5] R/PIO1_1/ 34 yes AD2/CT32B1_MAT0 [5] R/PIO1_2/ 35 yes AD3/CT32B1_MAT1 [5] ...
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... PIO2_0 — General purpose digital input/output pin DTR — Data Terminal Ready output for UART. I PIO2_1 — General purpose digital input/output pin DSR — Data Set Ready input for UART. I PIO2_2 — General purpose digital input/output pin DCD — Data Carrier Detect input for UART. I PIO2_3 — ...
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NXP Semiconductors Table 3. LPC1313/43 LQFP48 pin description table Symbol Pin Start logic input [7] XTALIN 6 - [7] XTALOUT [1] Pin state at reset for default function: ...
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... C Fast-mode Plus is selected in the I/O configuration register. I PIO0_6 — General purpose digital input/output pin USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor under software control. Used with the SoftConnect USB feature (LPC1342/43 only). I/O - SCK — Serial clock for SSP. I PIO0_7 — ...
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... PIO1_11 — General purpose digital input/output pin AD7 — A/D converter, input 7. I PIO2_0 — General purpose digital input/output pin DTR — Data Terminal Ready output for UART. I PIO3_2 — General purpose digital input/output pin. I PIO3_4 — General purpose digital input/output pin (LPC1311/13 only). I PIO3_5 — ...
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NXP Semiconductors Table 4. LPC1311/13/42/43 HVQFN33 pin description table Symbol Pin Start logic input [7] XTALIN 4 - [7] XTALOUT [1] Pin state at reset for default function: I ...
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... The interrupt vector area supports address remapping. The AHB peripheral area size and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for peripherals. Each peripheral of either type is allocated space. This allows simplifying the address decoding for each peripheral ...
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... Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.6.1 Features • Controls system exceptions and peripheral interrupts. • ...
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... Additionally, any GPIO pin (total pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.8.1 Features • Bit level port registers allow a single instruction to set or clear any number of bits in one write operation. • Direction control of individual bits. ...
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... The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, and endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers ...
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... The I C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed ...
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... The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt. ...
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... Clocking and power control 7.17.1 Integrated oscillators The LPC1311/13/42/43 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. LPC1311_13_42_43 Product data sheet × ...
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NXP Semiconductors Following reset, the LPC1311/13/42/43 will operate from the internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 7 IRC ...
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... MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. ...
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... WAKEUP pin. 7.18 System control 7.18.1 Start logic The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down ...
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... BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. An additional threshold level can be selected to cause a forced reset of the chip ...
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... NXP Semiconductors 7.18.5 Boot loader The boot loader controls initial operation after reset and also provides the means to program the flash memory. This could be initial programming of a blank device, erasure and re-programming of a previously programmed device, or programming of the flash memory by the application program in a running system. ...
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... The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted ...
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NXP Semiconductors 9. Static characteristics Table 7. Static characteristics = −40 °C to +85 °C, unless otherwise specified. T amb Symbol Parameter V supply voltage (core DD and external rail) I supply current DD Standard port pins and RESET pin; ...
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... C-bus pins (PIO0_4 and PIO0_5); see V HIGH-level input IH voltage V LOW-level input voltage IL V hysteresis voltage hys V LOW-level output OL voltage I input leakage current LI Oscillator pins V crystal input voltage i(xtal) V crystal output voltage o(xtal) USB pins (LPC1342/43 only) I OFF-state output OZ current LPC1311_13_42_43 Product data sheet … ...
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... IRC enabled; system oscillator disabled; system PLL disabled. [3] I measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. DD [4] BOD disabled. [5] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART, SSP, trace clock, and SysTick timer disabled in the syscon block ...
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... LPC1311_13_42_43 Product data sheet …continued Conditions ) is the difference between the actual step width and the ideal step width. See ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after Figure 8. Figure Figure 8. = 4.5 MHz and analog input capacitance C s × ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 8. ADC characteristics LPC1311_13_42_43 Product data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ...
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... Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC13xx user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. ...
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NXP Semiconductors (mA) Fig 9. (mA) Fig 10. Typical supply current versus temperature in Active mode LPC1311_13_42_43 Product data sheet MHz MHz 36 MHz 9 24 MHz 6 12 MHz 3 2.0 2.4 ...
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NXP Semiconductors (mA) Fig 11. Typical supply current versus temperature in Sleep mode (μA) Fig 12. Typical supply current versus temperature in Deep-sleep mode (analog blocks LPC1311_13_42_43 Product data sheet 10 72 MHz MHz 6 36 ...
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... Fig 13. Typical supply current versus temperature in Deep power-down mode 9.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG or PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed ...
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NXP Semiconductors Table 10. Power consumption for individual analog and digital blocks Peripheral Typical supply current in mA n/a 12 MHz GPIO - 0.21 IOCONFIG - 0.00 I2C - 0.03 ROM - 0.04 SSP - 0.11 UART - 0.20 WDT ...
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NXP Semiconductors (mA) Fig 15. I (mA) Fig 16. Typical LOW-level output current I LPC1311_13_42_43 Product data sheet 0.2 Conditions 3 pins PIO0_4 and PIO0_5 C-bus pins ...
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NXP Semiconductors V Fig 17. Typical HIGH-level output voltage V (μA) Fig 18. Typical pull-up current I LPC1311_13_42_43 Product data sheet 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions: V ...
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NXP Semiconductors (μA) Fig 19. Typical pull-down current I LPC1311_13_42_43 Product data sheet ° °C −40 ° Conditions 3.3 V; standard port pins ...
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... CHCL [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [2] Fig 20. External clock timing (with an amplitude of at least V LPC1311_13_42_43 Product data sheet Conditions powered unpowered ...
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... Dynamic characteristics: Watchdog oscillator Symbol Parameter f internal oscillator frequency osc [1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages. [2] The typical frequency spread over processing and temperature (T [3] See the LPC13xx user manual. LPC1311_13_42_43 Product data sheet ≤ 3.6 V [1] . ...
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... SCL; applies to data in transmission and the acknowledge. HD;DAT [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V bridge the undefined region of the falling edge of SCL. [ total capacitance of one bus line in pF ...
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... UM10204). This maximum must only be met if the device does not stretch the LOW period (t VD;ACK SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [ the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the SU;DAT acknowledge. 2 [10] A Fast-mode I C-bus device can be used in a Standard-mode I This will automatically be the case if the device does not stretch the LOW period of the SCL signal ...
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NXP Semiconductors 10.6 SSP interface Table 17. Dynamic characteristics: SSP pins in SPI mode Symbol Parameter SSP master T clock cycle time cy(clk) t data set-up time DS t data hold time DH t data output valid time v(Q) t ...
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NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 23. SSP master timing in SPI mode LPC1311_13_42_43 Product data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID ...
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NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 24. SSP slave timing in SPI mode LPC1311_13_42_43 Product data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA ...
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NXP Semiconductors 10.7 USB interface (LPC1342/43 only) Table 18. Dynamic characteristics: USB pins (full-speed pF 1.5 kΩ Symbol Parameter t rise time r t fall time f t differential ...
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NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions (LPC1342/43 only) LPC134x Fig 26. LPC1342/43 USB interface on a self-powered device LPC134x Fig 27. LPC1342/43 USB interface on a bus-powered device 11.2 XTAL input The input voltage to the ...
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... NXP Semiconductors Fig 28. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. ...
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... Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. LPC1311_13_42_43 Product data sheet Recommended values for C ...
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... Standard I/O pad configuration Figure 30 • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input pin configured as digital output pin configured as digital input pin configured as analog input Fig 30 ...
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... Reset pad configuration Fig 31. Reset pad configuration 11.6 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC1311/13/42/43 chip. • ...
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... NXP Semiconductors 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 0.85 mm terminal 1 index area terminal 1 32 index area Dimensions (1) Unit max 1.00 0.05 0.35 mm nom 0.85 0.02 0.28 0.2 min 0.80 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Advanced Peripheral Bus BrownOut Detection End Of Packet Embedded Trace Macrocell First-In, First-Out General Purpose Input/Output Human Interface Device Input/Output Least Significant Bit Mass Storage Class Physical Layer Phase-Locked Loop Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port ...
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... NXP Semiconductors 14. Revision history Table 22. Revision history Document ID Release date LPC1311_13_42_43 v.3 20100810 Modifications: LPC1311_13_42_43 v.2 20100506 LPC1311_13_42_43 v.1 20091211 LPC1311_13_42_43 Product data sheet Data sheet status Product data sheet • limit changed to −6500 V (min) /+6500 V (max ESD • Reset state of pins and start logic functionality added in • ...
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... NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’ ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s 16. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC1311_13_42_43 Product data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... SSP serial I/O controller . . . . . . . . . . . . . . . . . 20 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 7.12 I C-bus serial I/O controller . . . . . . . . . . . . . . 20 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14 General purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.15 System tick timer . . . . . . . . . . . . . . . . . . . . . . 22 7.16 Watchdog timer 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.17 Clocking and power control . . . . . . . . . . . . . . 22 7 ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: LPC1311_13_42_43 All rights reserved ...