BMA250 Bosch Sensortec, BMA250 Datasheet - Page 45
Manufacturer Part Number
3-AXIS ACCELEROMETER DIGITAL I/F
Specifications of BMA250
BMA250 - Digital, Triaxial Acceleration Sensor
X, Y, Z
±2g, 4g, 8g, 16g
256LSB/g, 128LSB/g, 64LSB/g, 16LSB/g
Voltage - Supply
1.62 V ~ 3.6 V
8Hz ~ 1kHz
Package / Case
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With
828-1024 - BMA250 DAUGHTERCARD FOR DEV KIT
Register (0x21) contains the interrupt reset bit and the interrupt mode selection. Writing ´1´ to
(0x21) reset_int resets any latched interrupt.
The settings for (0x21) latch_int are ´0000b´ (non-latched), ´0001b´ (temporary, 250 ms),
´0010b´ (temporary, 500 ms), ´0011b´ (temporary, 1 s), ´0100b´ (temporary, 2 s), ´0101b´
(temporary, 4 s), ´0110b´ (temporary, 8 s), ´0111b´ (latched), ´1000b´ (non-latched), ´1001b´
(temporary, 500 s), ´1010b´ (temporary, 500 s), ´1011b´ (temporary, 1 ms), ´1100b´
(temporary, 12.5 ms), ´1101b´ (temporary, 25 ms), ´1110b´ (temporary, 50 ms), ´1111b´
Default value of (0x21) latch_int is ´0000b´.
Register (0x22) contains the delay time definition for the low-g interrupt. The physical delay
time can be computed from the content of (0x22) low_dur according to:
delay [ms] = [(0x22) low_dur + 1] • 2 ms.
Possible delay times range from 2 ms to 512 ms. Default value of (0x22) low_dur is 0x09,
corresponding to a delay of 20 ms.
Register (0x23) contains the threshold definition for the low-g interrupt. An LSB of (0x23)
low_th corresponds to an actual acceleration of 7.81 mg. Therefore, the threshold ranges from 0
g to 1.992 g. Default value of (0x23) low_th is 0x30, corresponding to an acceleration of 375
Register (0x24) contains the low-g interrupt mode selection, the low-g interrupt hysteresis
setting, and the high-g interrupt hysteresis setting. Setting (0x24) low_mode to ´0´ (´1´) selects
´single´ mode (´sum´ mode). Default value is ´0´ (´single´ mode).
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as copying and passing on to third parties. BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany.
Note: Specifications within this document are subject to change without notice.
Table 46: Interrupt reset bit and interrupt mode selection, register (0x21)
Table 47: Delay time definition for the low-g interrupt, register (0x22)
Table 48: Threshold definition for the low-g interrupt, register (0x23)
Page 45 / not for publishing
03 March 2011