HSDL-3210-021 Lite-On Electronics, HSDL-3210-021 Datasheet - Page 17

• Manufacturer Part Number: HSDL-3210-021
• Description: TXRX IR 1.15MBIT/S 3V MIR SMD
• Manufacturer: Lite-On Electronics

Specifications of HSDL-3210-021

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

17
STC Bus Protocol and Timing
Diagrams
Bus Protocol
A set of commands is provided to
handle the various transactions
between the master and the slave.
The general format is shown in
Figure 19 whereby communica-
tions consist of a mandatory
command phase followed by an
optional response phase. The
response phase occurs only when
the slave needs to respond to a
command.
The command format consists of
either 2 or 3 bytes command.
The first byte, which is manda-
tory and common to all trans-
actions, consists of the address/
index/control bits. There are two
control fields. The first one is the
“C” field which determines
whether the command is a read
or write operation or to act as a
qualifier for a special operation.
The second one is the “INDX”
field whereby certain patterns
define Special Transactions while
others are for normal Data Trans-
actions. The “ADDR” field is used
to specify which transceiver the
command is for. In a single
transceiver system, this field is
set to “000”.
The second byte contains the
data payload for a 2 byte com-
mand. For a 3 byte command,
this second byte is an 8 bit
extended index.
The third byte is the data payload
when the extended index is used.
Figure 19. General command format.
Write Transactions
Write transactions are when the
master writes data to the slave to
select the slave’s operational
mode. This requires only the
command phase as shown below.
Figure 20. Write command phase format.
Read Transactions
Read transactions occur when the
master queries the internal regis-
ters of the slave. The initial com-
mand phase is always followed by
the response phase from the
slave as shown below.
Figure 21a. Read command phase format.
Figure 21b. Slave response format.
7
7
7
ADDR [2:0]
ADDR [2:0]
ADDR [2:0]
ADDR [2:0]
ADDR (3)
DATA
DATA (SLAVE RESPONSE) or E_INDX (8)
DATA (SLAVE RESPONSE) (8)
1
1
INDX [3:0]
INDX [3:0]
1
1
INDX (4)
1
1
1
1
0
1
0
1
C (1)
E_INDX[7:0]
E_INDX[7:0]
DATA
0
0
0
2nd BYTE
3rd BYTE
1st BYTE
DATA