HSDL-3210-021 Lite-On Electronics, HSDL-3210-021 Datasheet - Page 18

• Manufacturer Part Number: HSDL-3210-021
• Description: TXRX IR 1.15MBIT/S 3V MIR SMD
• Manufacturer: Lite-On Electronics

Specifications of HSDL-3210-021

• Lead Free Status / Rohs Status: Contains lead / RoHS non-compliant

18
Bus Timing Diagrams
The bus timings are designed to
be simple and to minimize the
effects of timing skew. This sec-
tion discusses some key points
with regard to bus timings and
illustrates typical STC transac-
tions with the use of waveforms.
Bus Timing Notes
1. Data is transferred in Little
2. There are no gaps between bytes
3. Each byte in the command and
4. For data sampling and clocking,
Endian order, that is, the LSB
on the first byte is transmitted
first and the MSB of the second
or third byte is transmitted last.
in the command or response
phases.
response phase is preceded by a
start bit on the SCLK line.
4.1. Input data is sampled on
4.2. Output data from the con-
4.3. Output data from the slave
the rising edge of SCLK.
troller is clocked out on the
falling edge of SCLK.
is clocked out on the rising
edge of SCLK.
5. The first low-to-high transition
6. The LED is re-enabled (by the
7. The response from the slave is
of SCLK indicates that an STC
transition is pending. On re-
ceipt of his rising edge, the slave
will disable the LED. The next
SCLK low-to-high transition
indicates the start cycle, fol-
lowed by the command phase
(which the controller puts out
on the SWDAT line). The LED
needs to be disabled since TXD
and SWDAT are multiplexed. If
the LED is not disabled, then
the LED will pulse according to
the SWDAT bit stream.
slave) on the last SCLK of the
STC transaction bit stream.
Normal infrared transmission
can resume. No SCLK transi-
tions should take place until the
next STC transaction else the
LED will be disabled.
carried on the SRDAT line,
which is multiplexed with RXD.
The detector is (internally) dis-
abled by the slave during the
response phase. This is to pre-
vent stray IR transitions from
corrupting the SRDAT bit
stream.
8. During a READ transaction, the
9. When powered up, the trans-
The transceiver is in STC mode
and ready to accept STC
transactions.
controller holds the SWDAT line
low for 1 clock after sending the
ADDRESS and INDEX byte. It
then holds it high and low for 3
clocks before the end of the
transaction. This is to allow the
transceiver to monitor the im-
pending end of a transaction
rather than by counting pulses.
ceiver is not ready to perform IR
transmissions. The controller
has to initialize the transceiver.
The brief powered up sequences
are:
9.1. On power up, an inter-
9.2. The controller has to initial-
nally generated signal in the
transceiver sets the 3 con-
trol registers:
a) Control Register 0:
b) Control Register 1:
c) Control Register 2:
ize the transceiver by:
a) Hold SWDAT low
b) Toggle SCLK for at least
• Bit 0: shutdown mode
• Bit 1: RXD disabled
• Bit 2: LED disabled
• Bit 0-7: SIR mode
• Bit 0-7: Power at 100%
30 cycles
level