LFXP20E-3FN256C Lattice, LFXP20E-3FN256C Datasheet - Page 170

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LFXP20E-3FN256C

Manufacturer Part Number
LFXP20E-3FN256C
Description
IC FPGA 19.7KLUTS 188I/O 256-BGA
Manufacturer
Lattice
Datasheet

Specifications of LFXP20E-3FN256C

Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-5. Example Generating Pseudo Dual Port RAM (RAM_DP) Using IPexpress
In the right-hand pane, options like Macro Type, Version, and Module_Name are device and selected module
dependent. These cannot be changed in IPexpress.
Users can change the directory where the generated module files will be placed by clicking the browse button in
the Project Path.
The File Name text box allows users to specify the entity and file name for the module they are about to generate.
Users must provide this name.
Design Entry, Verilog or VHDL, by default is the same as the project type. If the project is a VHDL project, the
selected Design Entry option will be “Schematic/ VHDL”, and “Schematic/ Verilog-HDL” if the project type is Verilog-
HDL.
Then click the Customize button. This opens another window where the RAM can be customized.
The the left-hand side of this window shows the block diagram of the module. The right-hand side includes the
Configuration tab.
9-5

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