LFXP20E-3FN256C Lattice, LFXP20E-3FN256C Datasheet - Page 365

• Manufacturer Part Number: LFXP20E-3FN256C
• Description: IC FPGA 19.7KLUTS 188I/O 256-BGA
• Manufacturer: Lattice

Specifications of LFXP20E-3FN256C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Therefore:
Assumptions for write set-up and hold equations:
Therefore:
Write Hold
Therefore:
Assumptions for write set-up and hold equations:
Therefore:
Address and Command Signals
Address (ddr_ad) and command signals (ddr_cas, ddr_ras, ddr_we) should meet set-up (t
timings at DDR interface with respect to positive edge of ddr_clk. Address and command signals are clocked
using negative edge of pll_mclk inside the FPGA as shown below. The ddr_clk signal is a delayed by pad
delay and board delay at DDR interface compared to pll_mclk inside the FPGA. As a result, 1/2clkx of set-up
and hold is provided by design.
Clock Delay - Data Delay > 0
t
1. t
2. t
1/2 clk2x - t
3.75/2 - 0.75 > 0
1.125 > 0
Data Delay = t
Clock Delay = t
Data Delay - Clock Delay > 0
t
1. t
2. t
1/2 clk2x - t
3.75/2 - 0.75 > 0
1.125 > 0
CDQS
CDQS
BDDS
CDQ
BDDS
CDQ
+ 1/2 clk2x - t
+ 1/2 clk2x - t
and t
and t
and t
and t
CDQS
CDQS
BDD
DS
BDD
DH
CDQ
CDQS
> 0
> 0
are equal (board delays are same both for dqs_out and ddr_dq_out).
are equal (board delays are same both for dqs_out and ddr_dq_out).
are equal (both are output delays from I/O flop).
are equal (both are output delays from I/O flop).
+ t
+ 1/2 clk2x + t
DS
BDD
DH
+ t
+ t
BDDS
BDDS
- t
- t
CDQ
CDQ
DH
- t
- t
+ t
BDD
BDD
BDDS
> 0
> 0
18-5
for the DDR SDRAM Controller IP Core
Board Timing Guidelines
DS
) and hold (t
DH
)