LFXP20E-3FN256C Lattice, LFXP20E-3FN256C Datasheet - Page 245

• Manufacturer Part Number: LFXP20E-3FN256C
• Description: IC FPGA 19.7KLUTS 188I/O 256-BGA
• Manufacturer: Lattice

Specifications of LFXP20E-3FN256C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
--*************BIDIRECTIONAL BUFFERS*****************************************************
--***************************************************************************************
--*************DDRInput******************************************************************
--DQSDLL, generates the DQS delay
--DDR INPUT primitives
signal clkinv : std_logic;
signal ddrclk : std_logic;
begin
vcc_net <= '1';
gnd_net <= '0';
clkinv<= not clk;
ddrclkpol<=ddrclkpol_sig;
bidiInst0 : BB PORT MAP( I => ddrout(0),T => tridata(0),O => ddrin(0),B => dq(0));
bidiInst1 : BB PORT MAP( I => ddrout(1),T => tridata(1),O => ddrin(1),B => dq(1));
bidiInst2 : BB PORT MAP( I => ddrout(2),T => tridata(2),O => ddrin(2),B => dq(2));
bidiInst3 : BB PORT MAP( I => ddrout(3),T => tridata(3),O => ddrin(3),B => dq(3));
bidiInst4 : BB PORT MAP( I => ddrout(4),T => tridata(4),O => ddrin(4),B => dq(4));
bidiInst5 : BB PORT MAP( I => ddrout(5),T => tridata(5),O => ddrin(5),B => dq(5));
bidiInst6 : BB PORT MAP( I => ddrout(6),T => tridata(6),O => ddrin(6),B => dq(6));
bidiInst7 : BB PORT MAP( I => ddrout(7),T => tridata(7),O => ddrin(7),B => dq(7));
bidiInst8 : BB PORT MAP( I=> dqsout, T=> tridqs, O=> dqsin, B=> dqs);
I0: DQSDLL PORT MAP(CLK=>clk, UDDCNTL=> uddcntl, RST=> reset, DQSDEL=> dqsdel,
I1: DQSBUFB PORT MAP( DQSI=> dqsin, CLK=>clk, READ=> read, DQSDEL=> dqsdel,
I2 : IDDRXB PORT MAP(D=> ddrin(0), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
I3 : IDDRXB PORT MAP(D=> ddrin(1), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
I4 : IDDRXB PORT MAP(D=> ddrin(2), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
I5 : IDDRXB PORT MAP(D=> ddrin(3), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
I6 : IDDRXB PORT MAP(D=> ddrin(4), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
I7 : IDDRXB PORT MAP(D=> ddrin(5), ECLK=> dqsbuf, SCLK => clk, CE => vcc_net,
LOCK => lock);
DDRCLKPOL=> ddrclkpol_sig, DQSC=> dqsc, PRMBDET=> prmbdet,
DQSO=> dqsbuf);
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(0),
QB => datain_n(0));
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(1),
QB => datain_n(1));
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(2),
QB => datain_n(2));
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(3),
QB => datain_n(3));
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(4),
QB => datain_n(4));
DDRCLKPOL=> ddrclkpol_sig, LSR => reset, QA =>datain_p(5),
QB => datain_n(5));
10-26
LatticeECP/EC and LatticeXP
DDR Usage Guide