LFXP20E-3FN256C Lattice, LFXP20E-3FN256C Datasheet - Page 233

• Manufacturer Part Number: LFXP20E-3FN256C
• Description: IC FPGA 19.7KLUTS 188I/O 256-BGA
• Manufacturer: Lattice

Specifications of LFXP20E-3FN256C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-15. Postamble Solution with Extra READ Command
Memory Write Implementation
To implement the write portion of a DDR memory interface, two streams of single data rate data must be multi-
plexed together with data transitioning on both edges of the clock. In addition, during a write cycle, DQS must arrive
at the memory pins center-aligned with data, DQ. Along with the strobe and data this portion of the interface pro-
vides the CLKP, CLKN Address/Command and Data Mask (DM) signals to the memory.
LatticeECP/EC and LatticeXP devices contain DDR output and tri-state registers along with PLLs that allow the
easy implementation of the write portion of the DDR memory interfaces. The DDR output registers can be
accessed in the design tools via the ODDRXB primitive.
All DDR output signals (“ADDR, CMD”, DQS, DQ, DM) are initially aligned to the rising edge of CLK inside the
FPGA core. These signals are used for the entire DDR write interface or the controls of DDR read interface. The
relative phase of the signals may be adjusted in the IOL logic before departing the FPGA. The adjustments are
shown in Figure 16
The adjustments are as follows:
The PLL is used to generate a 90 degree phase shifted clock. This 90 degree phase shifted clock will be used to
generate DQS and the differential clocks going to the memory.
The CLKP needs to be centered relative to the ADDR,CMD signal, which is an SDR signal. This is accomplished
by inverting the CLKP signal relative to the PLL’s 90 degree phase shifted CLK.
The DDR clock can be generated by assigning “0” to the DA input and “1” to the DB inputs of the ODDRXB primi-
tive as shown in Figure 10-16. This is then fed into a SSTL25 differential output buffer to generate CLKP and CLKN
differential clocks. Generating the CLKN in this manner would prevent any skew between the two signals.
The DDR interface specification for t
hold times must be met. This is met by making CLKP and DQS identical in phase. DQS is inverted to match CLKP
(= CLK + 270). This is accomplished by routing the positive DQS data in core logic to DB, and negative DQS data
in core logic to DA inputs of the ODDRXB primitive.
DQS at PIN
DQS at IOL
DATAIN_N
DATAIN_P
DQ at PIN
DQ at IOL
synce reg
CLK at
C
A
B
DSS
and t
DSH
parameters, defined as DQS falling to CLKP rising setup and
P0
P0
10-14
P0
N0
N0
P1
P1
N0
P0
P1
P0
N0
N1
N1
LatticeECP/EC and LatticeXP
N1
P1
N1
P1
DDR Usage Guide