PPC405GPR-3BB400 Applied Micro Circuits Corporation, PPC405GPR-3BB400 Datasheet - Page 35

• Manufacturer Part Number: PPC405GPR-3BB400
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GPR-3BB400

• Family Name: 405GPr
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/1.85V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7/1.8V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / Rohs Status: Not Compliant

Revision 2.05 – March 24, 2008
Signal Functional Description
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 29.
AMCC
Interrupts Interface
JTAG Interface
System Interface
IRQ0:6[GPIO17:23]
UART1_DSR/
UART1_RTS/
Signal Name
UART1_DTR
UART1_CTS
UART1_Tx
SysReset
IICSDA
IICSCL
SysClk
SysErr
AGND
TRST
AV
TMS
TDO
Data Sheet
TCK
Halt
TDI
DD
UART1 Serial Data Out.
UART1 Data Set Ready
or
UART1 Clear To Send. To access this function, software must toggle
a DCR bit.
UART1 Request To Send
or
UART1 Data Terminal Ready. To access this function, software must
toggle a DCR bit.
IIC Serial Clock.
IIC Serial Data.
Interrupt requests
or
General Purpose I/O. To access this function, software must toggle a
DCR bit.
Test data in.
JTAG test mode select.
Test data out.
JTAG test clock. The frequency of this input can range from DC to
25MHz.
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller and for normal operation of the PPC405GPr.
Main system clock input.
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
(two states; 0 or open circuit).
Clean voltage input for the PLL.
Clean Ground input for the PLL.
Set to 1 when a Machine Check is generated.
Halt from external debugger.
(Sheet 6 of 8)
Description
405GPr – Power PC 405GPr Embedded Processor
I[I/O]
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
Type
Notes
1, 2
1, 2
1, 4
1, 4
1, 4
1, 2
1, 2
6
1
6
1
5
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