PPC405GPR-3BB400 Applied Micro Circuits Corporation, PPC405GPR-3BB400 Datasheet - Page 55

• Manufacturer Part Number: PPC405GPR-3BB400
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GPR-3BB400

• Family Name: 405GPr
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/1.85V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7/1.8V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / Rohs Status: Not Compliant

Revision 2.05 – March 24, 2008
Revision Log
AMCC
PPC405GPr New Mode Strapping Pin Assignments
PCI Asynchronous Mode
Enable
External Bus Synchronous
Mode Enable
PCI Arbiter Enable
New Mode Enable
In Legacy mode the
PPC405GPr functions like the
PPC405GP.
If not strapped, the PPC405GPr
defaults to Legacy mode.
Flip Circuit Disable
(must be strapped low (0)
during initilization).
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using
4. The pull-up initialization strapping resistor must be 1kΩ rather than 3kΩ in order to overcome the internal pull-down resistor.
PPC405GPr. These bits are shown for information only; and do not require modification except in special clocking circumstances such as
spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GPr, visit the technical
documents area of the AMCC PowerPC web site.
Specifications” on page 43. Further requirements are detailed in the Clocking chapter of the PowerPC 405GPr Embedded Processor
User’s Manual.
three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
03/13/2003
08/28/2003
11/22/2004
12/02/2004
01/06/2005
08/29/2005
03/13/2007
09/07/2007
03/24/2008
Data Sheet
Function
Date
3
3
400MHz part numbers and new power/current numbers
Add new V
Correct package drawings and add lead-free part numbers.
Add +105
Add 1 ms. voltage ramp-up restriction.
Update to AMCC format.
Correct typographical error in 27mm package drawing.
Add dashes back into PNs.
Revise package drawings to add logo view.
Update AMCC address and copyright date on last page.
Change TestEn signal from active low to active high.
Correct AMCC telephone numbers.
Implement Doc Issue 496 (remove I/O timing for EMCMDIO signal).
Legacy (PPC405GP) mode
New (PPC405GPr) mode
°
Internal Arbiter Disabled
Synchronous PCI Mode
Internal Arbiter Enabled
DD
C temperature specification.
Asynchronous Mode
Asynchronous Mode
Synchronous Mode
Normal operation
values for 400MHz parts.
Option
405GPr – Power PC 405GPr Embedded Processor
4
Contents of Modification
GPIO9[TrcClk]
GPIO3[TS1O]
GPIO4[TS2O]
GPIO24
ExtAck
AF18
AB3
A22
D20
Y3
0
1
0
1
0
1
0
1
0
(Sheet 3 of 3)
Ball Strapping
55