PPC405GPR-3BB400 Applied Micro Circuits Corporation, PPC405GPR-3BB400 Datasheet - Page 52

• Manufacturer Part Number: PPC405GPR-3BB400
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GPR-3BB400

• Family Name: 405GPr
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 400MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/1.85V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7/1.8V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / Rohs Status: Not Compliant

405GPr – Power PC 405GPr Embedded Processor
52
PPC405GPr Legacy Mode Strapping Pin Assignments
OPB Divider from PLB
PCI Divider from PLB
External Bus Divider from PLB
ROM Width
ROM Location
PCI Asynchronous Mode Enable
PCI Arbiter Enable
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using
PPC405GPr. These bits are shown for information only; and do not require modification except in special clocking circumstances such as
spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GPr, visit the technical
documents area of the AMCC PowerPC web site.
Specifications” on page 43. Further requirements are detailed in the Clocking chapter of the PowerPC 405GPr Embedded Processor
User’s Manual.
three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
3
Function
2, 3
2
2
PPC405GPr Peripheral Attach
Internal Arbiter Disabled
PPC405GPr PCI Attach
Synchronous PCI Mode
Internal Arbiter Enabled
Asynchronous Mode
16-bit ROM
32-bit ROM
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 2
Divide by 3
Divide by 4
Divide by 5
8-bit ROM
Reserved
Option
(Sheet 2 of 2)
GPIO4[TS2O]
GPIO1[TS1E]
UART1_Tx
EMCTxD1
EMCTxErr
HoldAck
ExtAck
AF18
AC2
D18
K25
L25
U2
Y3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
Revision 2.05 – March 24, 2008
Ball Strapping
Data Sheet
GPIO2[TS2E]
UART1_RTS/
UART1_DTR
EMCTxD0
EMCTxEn
AD2
C20
K23
J26
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AMCC