LMP90080MHE/NOPB National Semiconductor, LMP90080MHE/NOPB Datasheet
LMP90080MHE/NOPB
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LMP90080MHE/NOPB Summary of contents
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... True Continuous Background Calibration at all gains ■ In-Place System Calibration using Expected Value programming 5.0 Typical Application TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation LMP90080/LMP90079/ LMP90078/LMP90077 ■ Low-Noise programmable gain (1x - 128x) ■ Continuous background open/short and out of range sensor diagnostics ■ ...
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Block Diagram • True Continuous Background Calibration The LMP90080/LMP90079/LMP90078/LMP90077 feature a 16 bit ΣΔ core with continuous background calibration to com- pensate for gain and offset errors in the ADC, virtually elimi- nating any drift with time and temperature. ...
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General Description ......................................................................................................................... 1 2.0 Features ........................................................................................................................................ 1 3.0 Key Specifications ........................................................................................................................... 1 4.0 Applications .................................................................................................................................... 1 5.0 Typical Application ........................................................................................................................... 1 6.0 Block Diagram ................................................................................................................................ 2 7.0 Ordering Information ........................................................................................................................ 5 8.0 Connection Diagram ........................................................................................................................ 5 9.0 Pin ...
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CHANNEL CONFIGURATION REGISTERS ............................................................................ 52 18.5 CALIBRATION REGISTERS .................................................................................................. 56 18.6 SENSOR DIAGNOSTIC REGISTERS ..................................................................................... 57 18.7 SPI REGISTERS .................................................................................................................. 58 18.8 GPIO REGISTERS ............................................................................................................... 60 19.0 Physical Dimensions .................................................................................................................... 61 FIGURE 1. Block Diagram ......................................................................................................................... 2 FIGURE 2. ...
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... Ordering Information Product LMP90080 LMP90079 LMP90078 LMP90077 Order Code LMP90080MH/NOPB LMP90080MHE/NOPB LMP90080MHX/NOPB LMP90079MH/NOPB LMP90079MHE/NOPB LMP90079MHX/NOPB LMP90078MH/NOPB LMP90078MHE/NOPB LMP90078MHX/NOPB LMP90077MH/NOPB LMP90077MHE/NOPB LMP90077MHX/NOPB 8.0 Connection Diagram See Pin Descriptions for specific information regarding options LMP90079, LMP90078, and LMP90077. Channel Configuration 4 Differential / 7 Single-Ended ...
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Pin Descriptions Pin # Pin Name VIN0 - VIN2 (LMP90080, VIN3 - VIN5 LMP90079 (LMP90078, VIN3 - VIN5 LMP90077) 8 VREFP1 9 VREFN1 10 VIN6 / VREFP2 11 VIN7 ...
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... Absolute Maximum Ratings 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage, VA Digital I/O Supply Voltage, VIO Reference Voltage, VREF Voltage on Any Analog Input Pin to GND (Note ...
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Symbol Parameter 3V & 214. & 13. Gain Error 3V & 13. & ...
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Symbol Parameter REFERENCE INPUT VREFP Positive Reference Negative VREFN Reference Differential VREF VREF = VREFP - VREFN Reference Reference ZREF 3V / 13.42 / OFF / OFF / 1 Impedance 3V / 13. OFF / ON or ...
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Symbol Parameter EXCITATION CURRENT SOURCES CHARACTERISTICS (LMP90080/LMP90078 only) Excitation Current IB1, IB2 Source Output VA = VREF = 3V IB1/IB2 Tolerance VA = VREF = 5V IB1/IB2 Output VA = 3.0V & 5.0V, Compliance Range IB1/IB2 = 100 µA to ...
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TABLE 1. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain VIO = VREF = 3V ODR (SPS 1.6775 16 (16) 16 (16) 3.355 16 (16) 16 (16) 6.71 16 (16) 16 (16) 13.42 16 ...
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Timing Diagrams Unless otherwise noted, specified limits apply for VA = VIO = 3.0V. Boldface limits apply for T apply for T = +25°C. A Symbol Parameter f SCLK t SCLK High time CH t SCLK Low time CL ...
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Symbol Parameter t SCLK Rise time CLKR t SCLK Fall time CLKF SDI Setup time prior to an SCLK t rising edge DISU SDI Hold time after an SCLK rising t edge DIH Symbol Parameter SDO Access time after an ...
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Symbol Parameter SDO Disable time after either t DOD2 edge of SCLK Symbol Parameter SDO Enable time from the falling t DOE edge of the 8th SCLK t SDO Rise time DOR t SDO Fall time DOF Data Ready Bar ...
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Specific Definitions COMMON MODE REJECTION RATIO is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed. ...
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Typical Performance Characteristics VIO = VREF = 3.0V. The maximum and minimum values apply for T Noise Measurement without Calibration at Gain = 1 250 230 210 190 170 150 0 200 400 TIME (ms) Histogram ...
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Histogram without Calibration at Gain = 8 Noise Measurement without Calibration at Gain = 128 200 400 600 TIME (ms) Histogram without Calibration at Gain = 128 ...
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Noise vs. Gain without Calibration at ODR = 13.42 SPS Noise vs. Gain without Calibration at ODR = 214.65 SPS Offset Error vs. Temperature without Calibration at Gain = 1 300 250 200 150 100 50 0 ...
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Offset Error vs. Temperature without Calibration at Gain = -40 - TEMPERATURE (°C) Gain Error vs. Temperature without Calibration at Gain = 1 160 ...
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Digital Filter Frequency Response 0 -20 -40 -60 -80 1.7 SPS 3.4 SPS -100 6.7 SPS 13.4 SPS -120 1 10 FREQUENCY (Hz) INL at Gain = 5V, 13.4 SPS - ...
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Functional Description Throughout this datasheet, the LMP90080/LMP90079/ LMP90078/LMP90077 will be referred to as the LMP900xx. The LMP900xx is a low-power 16-Bit ΣΔ ADC with 4 fully dif- ferential / 7 single-ended analog channels for the LMP90080/ LMP90079 and 2 ...
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Selectable Gains (FGA & PGA) LMP900xx provides two types of gain amplifiers: a fixed gain amplifier (FGA) and a programmable gain amplifier (PGA). FGA has a fixed gain of 16x or it can be bypassed, while the PGA has ...
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The ODR is channel specific, which means that one channel can have one ODR, while another channel can have the same or a different ODR. Note that these ODRs are meant for a single channel con- version; the ODR needs ...
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Digital Filter The LMP900xx has a fourth order rotated sinc filter that is used to configure various ODRs and to reject power supply frequencies of 50Hz and 60Hz. The 50/60 Hz rejection is only effective when the device is ...
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SPS -70 -80 -90 -100 -110 -120 FIGURE 7. Digital Filter Response at 13.42 SPS 0 -40 -80 -120 0 200 400 600 800 FIGURE 8. Digital Filter Response, 26.83125 SPS and 53.6625 ...
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FIGURE 9. Digital Filter Response 107.325 SPS and 214.65 SPS If the internal CLK is not being used and the external CLK is not 3.5717 MHz, then the filter response would be the same ...
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GPIO (D0–D6) Pins D0-D6 are general purpose input/output (GPIO) pins that can be used to control external LEDs or switches. Only a high or low value can be sourced to or read from each pin. 16.2 CALIBRATION As seen ...
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LMP900xx’s offset and gain errors. The last known offset or gain calibration coefficients can come from two sources. The first source is the default coefficient which is pre-determined and burnt in ...
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CHx_SCAL_OFFSET register is filled-in with the System Calibration Offset coefficient. 4. The System Calibration Offset Coefficient Determination mode is automatically exited. 5. The computed calibration coefficient is accurate only to the effective resolution of the device and ...
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SENSOR INTERFACE The LMP90080/LMP90078 contains two excitation currents (IB1 & IB2) for sourcing external sensors, and the LMP900xx contain two burnout currents for sensor diagnostics. They are described in the next sections. 16.4.1 IB1 & IB2 - Excitation Currents ...
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The sensor diagnostic flags are SENDIAG_FLAGS register and are described in further de- tails below. SHORT_THLD_FLAG: The short circuit threshold flag is used to report a short-circuit condition set when the output voltage (VOUT) is within the absolute ...
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SERIAL DIGITAL INTERFACE A synchronous 4-wire serial peripheral interface (SPI) pro- vides access to the internal registers of LMP900xx via CSB, SCLK, SDI, SDO/DRDYB. 16.5.1 Register Address (ADDR) All registers are memory-mapped. A register address (ADDR) is composed of ...
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CSB - Chip Select Bar An SPI transaction begins when the master asserts (active low) CSB and ends when the master deasserts (active high) CSB. Each transaction might be separated by a subsequent one with a CSB deassertion, but ...
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As shown in Figure 22, the drdyb signal and SDO can be multiplexed on the same pin as their functions are mostly complementary. In fact, this is the default mode for the SDO/DRDYB pin. Figure 23 shows a timing protocol ...
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FIGURE 24. Timing Protocol for DrdybCase2 35 30169729 www.national.com ...
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DrdybCase3: Routing DRDYB to D6 The drdyb signal can be routed to pin D6 by setting SPI_DRDYB_D6 high and SDO_DRDYB_DRIVER to 0x4. This is the behavior for DrdybCase3 as shown in The timing protocol for this case can be seen ...
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Note that while being in the data first mode, once the data bytes in the data only read transaction are sent out, the device is ready to start on any normal (non-data-only) transaction including the Disable Data First Mode Instruction. ...
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POWER MANAGEMENT The device can be placed in Active, Power-Down, or Stand- By state. In Power-Down, the ADC is not converting data, contents of the registers are unaffected, and there is a drastic power re- duction. In Stand-By, the ...
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Applications Information 17.1 QUICK START This section shows step-by-step instructions to configure the LMP900xx to perform a simple DC reading from CH0. 1. Apply VA = VIO = VREFP1 = 5V, and ground VREFN1 2. Apply VINP = ¾VREF ...
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REGISTER READ/WRITE EXAMPLES 17.4.1 Writing to Register Examples Using the register read/write protocol shown in register address (ADDR) 0x1F. After the last byte has been written to ADDR 0x21, deassert CSB to end the register-write. The next example shows ...
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Reading from Register Example The following example shows how to read two bytes. The first byte will be read from starting ADDR 0x24, and the second byte will be read from ADDR 0x25. FIGURE 33. Register-Read Example 41 30169739 ...
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STREAMING EXAMPLES 17.5.1 Normal Streaming Example This example shows how to write six data bytes starting at ADDR 0x28 using the Normal Streaming mode. Because the default STRM_TYPE is the Normal Streaming mode, setting up the SPI_STREAMCN register can ...
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Controlled Streaming Example This example shows how to read the 16-bit conversion data (ADC_DOUT) four times using the Controlled Streaming mode. The ADC_DOUT registers consist of ADC_DOUTH at ADDR 0x1A and ADC_DOUTL at ADDR 0x1B. The first step (Figure ...
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FIGURE 36. Controlled Streaming Example 44 30169794 ...
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EXAMPLE APPLICATIONS 17.6.1 3–Wire RTD FIGURE 37. Topology #1: 3-wire RTD Using 2 Current Sources Figure 37 shows the first topology for a 3-wire resistive tem- perature detector (RTD) application. Topology #1 uses two excitation current sources, IB1 and ...
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FIGURE 38. Topology #2: 3-wire RTD Using 1 Current Source Figure 38 shows the second topology for a 3-wire RTD appli- cation. Topology #2 shows the same connection as topology #1, but without IB2. Although this topology eliminates a cur- ...
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Thermocouple and IC Analog Temperature The LMP900xx is also ideal for thermocouple temperature applications. Thermocouples have several advantages that make them popular in many industrial and medical applica- tions. Compare to RTDs, thermistors, and IC sensors, ther- mocouples are ...
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Registers 1. If written to, RESERVED bits must be written to only 0 unless otherwise indicated. 2. Read back value of RESERVED bits and registers is unspecified and should be discarded. 3. Recommended values must be programmed and forbidden ...
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Register Name CH6_INPUTCN CH6 Input Control CH6_CONFIG CH6 Configuration Reserved - SYSTEM CALIBRATION REGISTERS CH0_SCAL_OFFSET CH0 System Calibration Offset Coefficients Reserved - CH0_SCAL_GAIN CH0 System Calibration Gain Coefficients Reserved - CH0_SCAL_SCALING CH0 System Calibration Scaling Coefficients CH0_SCAL_BITS_SEL CH0 System Calibration ...
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SPI_RESET: SPI Reset Control (Address 0x02) Bit Bit Symbol [0] SPI_ RST PWRCN: Power Mode Control and Status (Address 0x08) Bit Bit Symbol [7:2] Reserved [1:0] PWRCN www.national.com Bit Description SPI Reset Enable 0x0 (default): SPI Reset ...
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ADC REGISTERS ADC_RESTART: ADC Restart Conversion (Address 0x0B) Bit Bit Symbol Bit Description [7:1] Reserved - Restart conversion 0 RESTART 1: Restart conversion. 14.2.1. ADC_AUXCN: ADC Auxiliary Control (Address 0x12) Bit Bit Symbol Bit Description 7 Reserved ...
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ADC_DOUT: 16-bit Conversion Data (two’s complement) (Address 0x1A - 0x1B) Address Name 0x1A ADC_DOUTH 0x1B ADC_DOUTL 0x1C Reserved Note: Repeat reads of these registers are allowed as long as such reads are spaced apart by at least 72 µs. ...
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CH_SCAN: Channel Scan Mode (Address 0x1F) Bit Bit Symbol Bit Description Channel Scan Select 0x0 (default): ScanMode0: Single-Channel Continuous Conversion [7:6] CH_SCAN_SEL 0x1: ScanMode1: One or more channels Single Scan 0x2: ScanMode2: One or more channels Continuous Scan 0x3: ScanMode3: ...
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CHx_INPUTCN: Channel Input Control (CH4 to CH6 for LMP90080/LMP90079 only) Register Address (hex): a. CH0: 0x20 b. CH1: 0X22 c. CH2: 0x24 d. CH3: 0x26 e. CH4: 0x28 f. CH5: 0x2A g. CH6: 0x2C Bit Bit Symbol 7 BURNOUT_EN ...
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CHx_CONFIG: Channel Configuration (CH4 to CH6 LMP90080/LMP90079 only) Register Address (hex): a. CH0: 0x21 b. CH1: 0x23 c. CH2: 0x25 d. CH3: 0x27 e. CH4: 0x29 f. CH5: 0x2B g. CH6: 0x2D Bit Bit Symbol Bit Description 7 Reserved ...
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CALIBRATION REGISTERS BGCALCN: Background Calibration Control (Address 0x10) Bit Bit Symbol [7:2] Reserved [1:0] BGCALN SCALCN: System Calibration Control (Address 0x17) Bit Bit Symbol [7:2] Reserved [1:0] SCALCN CHx_SCAL_OFFSET: CH0-CH3 System Calibration Offset Registers (Two's-Complement) ADDR ...
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CHx_SCAL_SCALING: CH0-CH3 System Calibration Scaling Coefficient Registers ADDR Name CH0 CH1 CH2 CH3 0x36 0x3E 0x46 0x4E CHx_SCAL_SCALING CHx_SCAL_BITS_SELECTOR: CH0-CH3 System Calibration Bit Selector Registers ADDR Name CH0 CH1 CH2 CH3 0x37 0x3F 0x47 0x4F CHx_SCAL_BITS_SELECTOR 18.6 SENSOR DIAGNOSTIC ...
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SPI REGISTERS SPI_HANDSHAKECN: SPI Handshake Control (Address 0x01) Bit Bit Symbol [7:4] Reserved [3:1] SDO_DRDYB_ DRIVER 0 SW_OFF_TRG SPI_STREAMCN: SPI Streaming Control (Address 0x03) Bit Bit Symbol 7 STRM_TYPE [6:0] STRM_ RANGE DATA_ONLY_1: Data Only Read ...
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DATA_ONLY_2: Data Only Read Control 2 (Address 0x0A) Bit Bit Symbol Bit Description [7:3] Reserved - [2:0] Number of bytes to be read out in Data Only mode. A value of 0x0 means read one byte DATA_ONLY_SZ and 0x7 means ...
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SPI_CRC_DAT: CRC Data (Address 0x1D ) Bit Bit Symbol [7:0] CRC_DAT 18.8 GPIO REGISTERS GPIO_DIRCN: GPIO Direction (Address 0x0E ) Bit Bit Symbol 7 Reserved x GPIO_DIRCNx GPIO_DAT: GPIO Data (Address 0x0F) Bit Bit Symbol 7 Reserved x ...
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Physical Dimensions Order Number LMP90080MH/NOPB, LMP90079MH/NOPB, LMP90078MH/NOPB, LMP90077MH/NOPB inches (millimeters) unless otherwise noted 28-Lead Molded Plastic TSSOP NS Package Number MO-153 61 www.national.com ...
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