LMP90080MHE/NOPB National Semiconductor, LMP90080MHE/NOPB Datasheet - Page 32

• Manufacturer Part Number: LMP90080MHE/NOPB
• Description: IC AFE 16BIT 214.6SPS 28-TSSOP
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LMP90080MHE/NOPB

• Number Of Bits: 16
• Number Of Channels: 4 Differential, 7 Single-Ended
• Power (watts): -
• Voltage - Supply, Analog: 2.85 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / Rohs Status: Compliant

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16.5 SERIAL DIGITAL INTERFACE
A synchronous 4-wire serial peripheral interface (SPI) pro-
vides access to the internal registers of LMP900xx via CSB,
SCLK, SDI, SDO/DRDYB.
16.5.1 Register Address (ADDR)
All registers are memory-mapped. A register address (ADDR)
is composed of an upper register address (URA) and lower
register address (LRA) as shown in
ADDR 0x3A has URA=0x3 and LRA=0xA.
16.5.3 Streaming
When writing/reading 3+ bytes, the user must operate the de-
vice in Normal Streaming mode or Controlled Streaming
mode. In the Normal Streaming mode, which is the default
mode, data runs continuously starting from ADDR until CSB
deasserts. This mode is especially useful when programming
all the configuration registers in a single transaction. See
Section 17.5.1 Normal Streaming Example
the Normal Streaming mode.
In the Controlled Streaming mode, data runs continuously
starting from ADDR until the data has run through all
(STRM_RANGE + 1) registers. For example, if the starting
ADDR is 0x1C, STRM_RANGE = 5, then data will be written
to or read from the following ADDRs: 0x1C, 0x1D, 0x1E,
Bit
Name
[6:4]
URA
ADDR Map
ADDR
[3:0]
LRA
Map. For example,
FIGURE 19. Register Read/Write Protocol
for an example of
32
16.5.2 Register Read/Write Protocol
Figure 19
register.
Transaction 1 sets up the upper register address (URA)
where the user wants to start the register-write or register-
read.
Transaction 2 sets the lower register address (LRA) and in-
cludes the Data Byte(s), which contains the incoming data
from the master or outgoing data from the LMP900xx.
Examples of register-reads or register-writes can be found in
Section 17.4 REGISTER READ/WRITE
0x1F, 0x20, 0x21. Once the data reaches ADDR 0x21, LM-
P900xx will wrap back to ADDR 0x1C and repeat this process
until CSB deasserts. See
ing Example
mode.
If streaming reaches ADDR 0x7F, then it will wrap back to
ADDR 0x00. Furthermore, reading back the Upper Register
Address after streaming will report the Upper Register Ad-
dress at the start of streaming, not the Upper Register Ad-
dress at the end of streaming.
To stream, write 0x3 to INST2’s SZ bits as seen in
19. To select the stream type, program the SPI_STREAMCN:
STRM_TYPE bit. The STRM_RANGE can also be pro-
grammed in the same register.
shows the protocol how to write to or read from a
for an example of the Controlled Streaming
Section 17.5.2 Controlled Stream-
EXAMPLES.
30169736
Figure