LMP90080MHE/NOPB National Semiconductor, LMP90080MHE/NOPB Datasheet - Page 22

• Manufacturer Part Number: LMP90080MHE/NOPB
• Description: IC AFE 16BIT 214.6SPS 28-TSSOP
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LMP90080MHE/NOPB

• Number Of Bits: 16
• Number Of Channels: 4 Differential, 7 Single-Ended
• Power (watts): -
• Voltage - Supply, Analog: 2.85 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / Rohs Status: Compliant

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16.1.3 Selectable Gains (FGA & PGA)
LMP900xx provides two types of gain amplifiers: a fixed gain
amplifier (FGA) and a programmable gain amplifier (PGA).
FGA has a fixed gain of 16x or it can be bypassed, while the
PGA has programmable gain settings of 1x, 2x, 4x, or 8x.
Total gain is defined as FGA x PGA. Thus, LMP900xx pro-
vides gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x
with true continuous background calibration.
The gain is channel specific, which means that one channel
can have one gain, while another channel can have the same
or a different gain.
The gain can be selected by programming the CHx_CONFIG:
GAIN_SEL bits.
16.1.4 Buffer (BUFF)
There is an internal unity gain buffer that can be included or
excluded from the signal path. Including the buffer provides a
high input impedance but increases the power consumption.
The recommended value for the external CLK is discussed in
the next sections.
16.1.6 Programmable ODRs
If using the internal CLK or external CLK of 3.5717 MHz, then
the output date rates (ODR) can be selected (using the
ODR_SEL bit) as:
1. 13.42/8 = 1.6775 SPS
2. 13.42/4 = 3.355 SPS
3. 13.42/2 = 6.71SPS
4. 13.42 SPS
5. 214.65/8 = 26.83125 SPS
6. 214.65/4 = 53.6625 SPS
7. 214.65/2 = 107.325 SPS
8. 214.65 SPS (default)
If the internal CLK is not being used and the external CLK is
not 3.5717 MHz, then the ODR will be different. If this is the
FIGURE 4. CLK Register Settings
22
When gain
signal path. When gain < 16, including or excluding the buffer
from the signal path can be done by programming the
CHX_CONFIG: BUF_EN bit.
16.1.5 Internal/External CLK Selection
LMP900xx allows two clock options: internal CLK or external
CLK (crystal (XTAL) or clock source).
There is an “External Clock Detection” mode, which detects
the external XTAL if it is connected to XOUT and XIN. When
operating in this mode, the LMP900xx shuts off the internal
clock to reduce power consumption. Below is a flow chart to
help set the appropriate clock registers.
case, use the equation below to calculate the new ODR val-
ues.
For example, a 3.6864 MHz XTAL or external clock has the
following ODR values:
ODR2 = (221.54 SPS) / n = 221.54, 110.77, 55.38, 27.69 SPS
ODR1 = (13.85 SPS) / n = 13.85, 6.92, 3.46, 1.73 SPS
ODR_Base1 = (3.6864 MHz) / (266,240) = 13.85 SPS
ODR_Base2 = (3.6864 MHz) / (16,640) = 221.54 SPS
ODR1 = (ODR_Base1) / n, where n = 1,2,4,8
ODR2 = (ODR_Base2) / n, where n = 1,2,4,8
≥
ODR_Base1 = (CLK
ODR_Base2 = (CLK
16, the buffer is automatically included in the
EXT
EXT
) / (266,240)
) / (16,640)
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