HEF40174BP NXP Semiconductors, HEF40174BP Datasheet

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HEF40174BP

Manufacturer Part Number
HEF40174BP
Description
Manufacturer
NXP Semiconductors
Type
Dr
Datasheet

Specifications of HEF40174BP

Logic Family
4000
Technology
CMOS
Number Of Bits
6
Number Of Elements
1
Clock-edge Trigger Type
Positive-Edge
Polarity
Non-Inverting
Operating Supply Voltage (typ)
3.3/5/9/12V
Package Type
PDIP
Propagation Delay Time
175ns
Output Type
Standard
Low Level Output Current
3.6mA
High Level Output Current
-3.6mA
Frequency (max)
11MHz
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
15V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
16
Lead Free Status / Rohs Status
Compliant

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1. General description
2. Features
3. Applications
4. Ordering information
Table 1.
All types operate from
Type number
HEF40174BP
HEF40174BT
Ordering information
Package
Name
DIP16
SO16
40
The HEF40174B is a hex edge-triggered D-type flip-flop with six data inputs (D0 to D5), a
clock input (CP), an overriding asynchronous master reset input (MR), and six buffered
outputs (Q0 to Q5). Information on D0 to D5 is transferred to Q0 to Q5 on the
LOW-to-HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (Q0 to
Q5 = LOW) independent of CP and D0 to D5.
It operates over a recommended V
(usually ground). Unused inputs must be connected to V
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.
°
C to +85
HEF40174B
Hex D-type flip-flop
Rev. 05 — 6 January 2010
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the full industrial temperature range −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
Industrial
Shift registers
Buffer/storage register
Pattern generator
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
°
C.
DD
power supply range of 3 V to 15 V referenced to V
DD
, V
SS
, or another input. It is
Product data sheet
Version
SOT38-4
SOT109-1
SS

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HEF40174BP Summary of contents

Page 1

... Table 1. Ordering information − ° All types operate from +85 Type number Package Name Description HEF40174BP DIP16 plastic dual in-line package; 16 leads (300 mil) HEF40174BT SO16 plastic small outline package; 16 leads; body width 3.9 mm power supply range referenced ° C. Product data sheet ...

Page 2

... NXP Semiconductors 5. Functional diagram FF1 Fig 1. Functional diagram Fig 2. Logic diagram HEF40174B_5 Product data sheet FF2 FF3 FF4 FF1 FF2 FF3 Rev. 05 — 6 January 2010 HEF40174B Hex D-type flip-flop FF5 FF6 001aae565 FF4 FF5 FF6 001aae567 © NXP B.V. 2010. All rights reserved. ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin MR 1 Q0, Q1, Q2, Q3, Q4 10, 12, 15 D0, D1, D2, D3, D4 11, 13 Functional description [1] Table 3. Function table Input CP D ↑ H ↑ L ↓ HIGH voltage level LOW voltage level don’t care; ↑ = positive-going transition; ↓ = negative-going transition. ...

Page 4

... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I input clamping current IK V input voltage I I output clamping current OK I input/output current I/O I supply current DD T storage temperature stg ...

Page 5

... NXP Semiconductors Table 6. Static characteristics …continued unless otherwise specified Symbol Parameter HIGH-level output voltage | LOW-level output voltage OL I HIGH-level output current LOW-level output current OL I input leakage current I I supply current DD C input capacitance I 11. Dynamic characteristics Table 7. Dynamic characteristics ° ...

Page 6

... NXP Semiconductors Table 7. Dynamic characteristics ° test circuit see SS amb Symbol Parameter Conditions t hold time Dn to CP; h see t pulse width CP input LOW; W minimum width; see MR input LOW; minimum width; see t recovery time MR input; rec see f maximum frequency see max [ the same as t and t ...

Page 7

... NXP Semiconductors 12. Waveforms input input input PLH output TLH a. CP and Propagation delays and Qn transition times V CP input input input and MR minimum pulse widths recovery time, and set-up and hold times V and V are typical output voltage levels that occur with the output load. ...

Page 8

... NXP Semiconductors negative positive a. Input waveforms b. Test circuit Test data is given in Table 9. Definitions for test circuit: DUT = Device Under Test C = Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Z T Fig 5. Test circuit for measuring switching times Table 9 ...

Page 9

... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. max. 1.73 mm 4.2 0.51 3.2 1.30 0.068 inches 0.17 0.02 0.13 0.051 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors 14. Revision history Table 10. Revision history Document ID Release date HEF40174B_5 20100106 • Modifications: Section 9 “Recommended operating conditions” HEF40174B_4 20090813 HEF40174B_CNV_3 19950101 HEF40174B_CNV_2 19950101 HEF40174B_5 Product data sheet Data sheet status Change notice Product data sheet - Δt/ΔV values updated. ...

Page 12

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 13

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 Revision history ...

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