HEF4007UBP NXP Semiconductors, HEF4007UBP Datasheet - Page 2

• Manufacturer Part Number: HEF4007UBP
• Manufacturer: NXP Semiconductors

Specifications of HEF4007UBP

• Logic Family: 4000
• Logical Function: Complementary Pair
• Number Of Elements: 1
• Number Of Channels: 3
• Number Of Inputs: 3
• Number Of Outputs: 3
• Operating Supply Voltage (typ): 3.3/5/9/12V
• Package Type: PDIP
• Output Type: Standard
• Polarity: Inverting
• Propagation Delay Time: 80ns
• High Level Output Current: -3.6mA
• Low Level Output Current: 3.6mA
• Operating Supply Voltage (max): 15V
• Operating Supply Voltage (min): 3V
• Quiescent Current: 4uA
• Technology: CMOS
• Pin Count: 14
• Mounting: Through Hole
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
DESCRIPTION
The HEF4007UB is a dual complementary pair and an inverter with access to each device. It has three n-channel and
three p-channel enhancement mode MOS transistors.
January 1995
HEF4007UBP(N):
HEF4007UBD(F):
HEF4007UBT(D):
( ): Package Designator North America
Dual complementary pair and inverter
Fig.2 Pinning diagram.
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
Fig.1 Schematic diagram.
2
PINNING
FAMILY DATA, I
See Family Specifications for V
S
D
D
S
D
G
P2
P1
N1
N2
N/P3
1
to G
, S
, S
, D
, D
P3
N3
P2
N2
3
source connections to 2nd and 3rd
p-channel transistors
drain connections from the 1st and 2nd
p-channel transistors
drain connections from the 1st and 2nd
n-channel transistors
source connections to the 2nd and 3rd
n-channel transistors
common connection to the 3rd p-channel
and n-channel transistor drains
gate connections to n-channel and
p-channel of the three transistor pairs
DD
LIMITS category GATES
IH
/V
Product specification
IL
HEF4007UB
unbuffered stages
gates