PCF8562TT NXP Semiconductors, PCF8562TT Datasheet
PCF8562TT
Specifications of PCF8562TT
Available stocks
Related parts for PCF8562TT
PCF8562TT Summary of contents
Page 1
PCF8562 Universal LCD driver for low multiplex rates Rev. 02 — 22 January 2007 1. General description The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive ...
Page 2
... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Topside mark Package Name PCF8562TT PCF8562TT TSSOP48 4. Block diagram 21 V LCD LCD BIAS GENERATOR CLK CLOCK SELECT 12 AND TIMING SYNC 15 OSC OSCILLATOR SCL INPUT 10 FILTERS SDA Fig 1. Block diagram PCF8562_2 Product data sheet Description plastic thin shrink small outline package ...
Page 3
... S27 S28 S29 S30 S31 SDA SCL PCF8562_2 Product data sheet 1 S23 S24 2 S25 3 4 S26 5 S27 S28 6 S29 7 8 S30 S31 9 SDA 10 SCL 11 12 SYNC PCF8562TT CLK OSC SA0 LCD 22 BP0 23 BP2 BP1 24 Pin description Pin Description 1 LCD segment output ...
Page 4
... NXP Semiconductors Table 2. Symbol SYNC CLK V DD OSC SA0 LCD BP0 BP2 BP1 BP3 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 PCF8562_2 Product data sheet Pin description …continued Pin Description 12 cascade synchronization input and output ...
Page 5
... NXP Semiconductors 6. Functional description The PCF8562 is a versatile peripheral device designed to interface between any microprocessor/microcontroller and a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The display configurations possible with the PCF8562 depend on the number of active backplane outputs required. A selection of display confi ...
Page 6
... NXP Semiconductors 6.1 Power-on reset At power-on the PCF8562 resets to the following starting conditions: • All backplane outputs are set to V • All segment outputs are set to V • Drive mode ‘ multiplex with • Blinking is switched off • Input and output bank selectors are reset (as defined in • ...
Page 7
... NXP Semiconductors 6.3.1 LCD bias formulae Bias is calculated by the formula where for The LCD on voltage (V The LCD off voltage (V where static Discrimination is the ratio -------------- - = V OFF Using Equation 1.732 and the discrimination for an LCD drive mode with The advantage of these LCD drive modes is a reduction of the LCD full-scale voltage V as follows: • ...
Page 8
... NXP Semiconductors 6.4 LCD drive mode waveforms 6.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BP0) and segment drive (Sn) waveforms for this mode are shown in a. Waveforms at driver b. Resultant waveforms at LCD segment Fig 4 ...
Page 9
... NXP Semiconductors 6.4 multiplex drive mode The multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of Figure 6. a. Waveforms at driver b. Resultant waveforms at LCD segment Fig 5. Waveforms for the multiplex drive mode with ...
Page 10
... NXP Semiconductors a. Waveforms at driver b. Resultant waveforms at LCD segment Fig 6. Waveforms for the multiplex drive mode with PCF8562_2 Product data sheet V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD state LCD LCD V LCD ...
Page 11
... NXP Semiconductors 6.4 multiplex drive mode When three backplanes are provided in the LCD, the multiplex drive mode applies (see Figure a. Waveforms at driver b. Resultant waveforms at LCD segment Fig 7. Waveforms for the multiplex drive mode PCF8562_2 Product data sheet 7). V LCD LCD BP0 ...
Page 12
... NXP Semiconductors 6.4 multiplex drive mode When four backplanes are provided in the LCD, the multiplex drive mode applies (see Figure 8). PCF8562_2 Product data sheet Universal LCD driver for low multiplex rates Rev. 02 — 22 January 2007 PCF8562 © NXP B.V. 2007. All rights reserved. ...
Page 13
... NXP Semiconductors V LCD LCD BP0 LCD LCD LCD BP1 LCD LCD LCD BP2 LCD LCD LCD BP3 LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD Waveforms at driver state 1 state 2 b. Resultant waveforms at LCD segment V ( (t) V (t); V ...
Page 14
... NXP Semiconductors 6.5 Oscillator 6.5.1 Internal clock The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal oscillator external clock. The internal oscillator is enabled by connecting pin OSC to pin V 6.5.2 External clock Pin CLK is enabled as an external clock input by connecting pin OSC to V The LCD frame signal frequency is determined by the clock frequency (f A clock signal must always be supplied to the device ...
Page 15
... NXP Semiconductors 6.10 Display RAM The display RAM is a static 32 bit-map indicates the on-state of the corresponding LCD segment; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The fi ...
Page 16
Data pointer drive mode LCD segments LCD backplanes BP0 static ...
Page 17
... NXP Semiconductors The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the Load Data Pointer command. Following this, an arriving data byte is stored at the display RAM address indicated by the data pointer in accordance with the fi ...
Page 18
... NXP Semiconductors 6.15 Blinker The PCF8562 has a very versatile display blinking capability. The whole display can blink at a frequency selected by the Blink command. Each blink frequency is a multiple integer value of the clock frequency; the ratio between the clock frequency and blink frequency depends on the blink mode selected, as shown in Table 5 ...
Page 19
... NXP Semiconductors 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig 11. Bit transfer 7 ...
Page 20
... NXP Semiconductors 7.4 Acknowledge The number of data bytes that can be transferred from transmitter to receiver between the Start and Stop conditions is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal on the bus that is asserted by the transmitter during which time the master generates an extra acknowledge related clock pulse ...
Page 21
... NXP Semiconductors 2 7.7 I C-bus protocol 2 Two I C-bus slave addresses (01110000 and 01110010) are reserved for the PCF8562. The least significant bit of the slave address that a PCF8562 will respond to is defined by the level tied to its SA0 input. The PCF8562 is a write-only device and will not respond to a read access ...
Page 22
... NXP Semiconductors 7.8 Command decoder The command decoder identifies command bytes that arrive on the I commands carry a continuation bit C in their most significant bit position as shown in Figure 16. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command ...
Page 23
... NXP Semiconductors Table 8. LCD bias 1 bias 3 1 bias 2 Table 9. Display status Disabled (blank) Enabled Table 10. Description Six bit binary value Table 11. Description Three bit binary value Table 12. Static RAM bit 0 RAM bit 2 Table 13. Static RAM bit 0 RAM bit 2 Table 14. Blink frequency ...
Page 24
... NXP Semiconductors 7.9 Display controller The display controller executes the commands identified by the command decoder. It contains the device’s status registers and co-ordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order. ...
Page 25
... NXP Semiconductors 8. Device protection Fig 17. Device protection diagram PCF8562_2 Product data sheet Universal LCD driver for low multiplex rates V DD SA0 CLK OSC SYNC A0, A1 LCD BP0, BP1, BP2, BP3 LCD S0 to S31 V SS Rev. 02 — 22 January 2007 PCF8562 SCL V SS ...
Page 26
... NXP Semiconductors 9. Limiting values Table 17. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V LCD supply voltage LCD V input voltage i V output voltage O I input current I I output current O I supply current DD I ground current ...
Page 27
... NXP Semiconductors 10. Static characteristics Table 18. Static characteristics Symbol Parameter Supplies V supply voltage DD V LCD supply voltage LCD I supply current DD I LCD supply current LCD Logic V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I HIGH-level output current ...
Page 28
... NXP Semiconductors 11. Dynamic characteristics Table 19. Dynamic characteristics Symbol Parameter f oscillator frequency CLK t input CLK HIGH time CLKH t input CLK LOW time CLKL t SYNC propagation delay PD(SYNC) t SYNC LOW time SYNCL t driver delays with test loads PD(LCD) 2 [3] Timing characteristics: I C-bus ...
Page 29
... NXP Semiconductors BP0 to BP3, and S0 to S31 Fig 19. Driver timing waveforms SDA SCL SDA Fig 20. I PCF8562_2 Product data sheet 1/f CLK t CLKH CLK SYNC t PD(SYNC BUF LOW t HD;STA C-bus timing waveforms Rev. 02 — 22 January 2007 PCF8562 Universal LCD driver for low multiplex rates ...
Page 30
... NXP Semiconductors 12. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
Page 31
... NXP Semiconductors 13. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5 . 14. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
Page 32
... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 14.4 Reflow soldering Key characteristics in reflow soldering are: • ...
Page 33
... NXP Semiconductors Fig 22. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . PCF8562_2 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature ...
Page 34
... Document ID Release date PCF8562_2 20070122 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section • Table PCF8562_1 ...
Page 35
... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
Page 36
... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 LCD bias generator 6.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 6 6.3.1 LCD bias formulae . . . . . . . . . . . . . . . . . . . . . . 7 6.4 LCD drive mode waveforms . . . . . . . . . . . . . . . 8 6 ...