W39F010P-70B Winbond Electronics, W39F010P-70B Datasheet
W39F010P-70B
Specifications of W39F010P-70B
Available stocks
Related parts for W39F010P-70B
W39F010P-70B Summary of contents
Page 1
... Embedded Programming Algorithm ............................................................................. 14 7.4 Embedded Erase Algorithm.......................................................................................... 15 7.5 Embedded #Data Polling Algorithm.............................................................................. 16 7.6 Boot Block Lockout Enable Flow Chart ........................................................................ 17 7.7 Software Product Identification and Boot Block Lockout Detection Flow Chart........... 18 128K × 8 CMOS FLASH MEMORY Publication Release Date: December 26, 2005 - 1 - W39F010 Revision A4 ...
Page 2
DC CHARACTERISTICS.......................................................................................................... 19 8.1 Absolute maximum Ratings .......................................................................................... 19 8.2 DC Operating Characteristics....................................................................................... 19 8.3 Pin Capacitance............................................................................................................ CHARACTERISTICS .......................................................................................................... 20 9.1 AC Test Conditions....................................................................................................... 20 9.2 AC Test Load and Waveform ....................................................................................... 20 9.3 Read Cycle ...
Page 3
... GENERAL DESCRIPTION is a 1Mbit, 5-volt only CMOS flash memory organized as 128K × 8 bits. For flexible The W39F010 erase capability, the 1Mbits of data are divided into 32 small even pages with 4 Kbytes. The byte-wide (× 8) data appears on DQ7 − DQ0. The device can be programmed and erased in-system with a standard 5V power supply ...
Page 4
PIN CONFIGURATIONS NC A16 A15 A12 DQ0 DQ1 DQ2 Vss DQ0 1 A11 A13 4 5 A14 NC 6 ...
Page 5
BLOCK DIAGRAM VDD Vss #WE State Control Command Register #CE #OE VDD Detect Timer Erase Voltage Generator Program Voltage Generator Chip Enable Output Enable Logic A Y-Decode X-decode s ...
Page 6
PIN DESCRIPTION SYMBOL A0 − A16 DQ0 − DQ7 #CE #OE # PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connections - 6 - W39F010 ...
Page 7
FUNCTIONAL DESCRIPTION 6.1 Device Bus Operation 6.1.1 Read Mode The read operation of the W39F010 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is ...
Page 8
Boot Block Operation There are two alternatives to set the boot block. The 16K-byte in the top/bottom location of this device can be locked as boot block, which can be used to store boot codes located in ...
Page 9
... Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. 6.4.2 Auto-select Command Flash memories are intended for use in applications where the local CPU can alter memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. ...
Page 10
Chip Erase Command Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase command. Chip erase does not require ...
Page 11
Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the output enable (#OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that ...
Page 12
TABLE OF OPERATING MODES 7.1 Device Bus Operations MODE Read Write Standby Write Inhibit Output Disable 7.2 Command Definitions COMMAND NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE 7TH CYCLE (1) Description Cycles ...
Page 13
PA = 1FXXXh for Page 1EXXXh for Page 1DXXXh for Page 1CXXXh for Page 1BXXXh for Page 1AXXXh for Page 19XXXh for ...
Page 14
Embedded Programming Algorithm Increment Address Program Command Sequence (Address/Command): Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit No Last Address ? Yes Programming Completed 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 14 - W39F010 Pause T ...
Page 15
Embedded Erase Algorithm Write Erase Command Sequence #Data Polling or Toggle Bit Chip Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H 5555H/10H Start (see below) Successfully Completed Erasure Completed Individual Page Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H ...
Page 16
Embedded #Data Polling Algorithm 7.5 (DQ0 - DQ7) Address = VA No Embedded Toggle Bit Algorithm Yes Start VA = Byte address for programming = Any of the page addresses within Read Byte the page being erased during page erase ...
Page 17
Boot Block Lockout Enable Flow Chart Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 ...
Page 18
Software Product Identification and Boot Block Lockout Detection Flow Chart Product Identification Entry (1) Load data AA to address 5555 Load data 55 to address 2AAA Load data 90 to address 5555 μ Pause 10 S Notes for software ...
Page 19
DC CHARACTERISTICS 8.1 Absolute maximum Ratings PARAMETER Power Supply Voltage to V Potential SS Operating Temperature Storage Temperature Voltage on Any Pin to Ground Potential Except A9 Voltage on A9 Pin to Ground Potential Note: Exposure to conditions beyond ...
Page 20
AC CHARACTERISTICS 9.1 AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 9.2 AC Test Load and Waveform (Including Jig and Scope) Input <5 nS 1.5V/1.5V 1 TTL ...
Page 21
AC Characteristics, continued 9.3 Read Cycle Timing Parameters = 5V ±0.5V 0V 70° PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time #CE ...
Page 22
AC Characteristics, Continued 9.5 Power-up Timing PARAMETER Power-up to Read Operation Power-up to Write Operation 9.6 Data Polling and Toggle Bit Timing Parameters PARAMETER #OE to Data Polling Output Delay #CE to Data Polling Output Delay #OE to Toggle Bit ...
Page 23
TIMING WAVEFORMS 10.1 Read Cycle Timing Diagram Address A16-0 #CE # #WE High-Z DQ7-0 10.2 #WE Controlled Command Write Cycle Timing Diagram Address A16-0 #CE #OE #WE DQ7-0 Timing Waveforms, Continued ...
Page 24
Controlled Command Write Cycle Timing Diagram Address A16-0 #CE #OE #WE High Z DQ7-0 10.4 Chip Erase Timing Diagram Address A16-0 5555 DQ7-0 #CE #OE T #WE SB0 OES Six-byte code for ...
Page 25
Timing Waveforms, Continued 10.5 Page Erase Timing Diagram 5555 Address A16-0 DQ7-0 #CE #OE T #WE SB0 PA = Page Address Please refer to page 9 for detail informatio 10.6 #DATA Polling Timing Diagram Address A16-0 An #WE #CE #OE ...
Page 26
Timing Waveforms, Continued 10.7 Toggle Bit Timing Diagram Address A16-0 #WE #CE #OE DQ6 T OEH W39F010 T OES ...
Page 27
... W39F010-90B 90 W39F010T-70B 70 W39F010T-90B 90 W39F010Q-70B 70 W39F010Q-90B 90 W39F010P-70B 70 W39F010P-90B 90 W39F010P-70Z 70 W39F010P-90Z 90 Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ...
Page 28
... HOW TO READ THE TOP MARKING Example: The top marking of 32-pin PLCC W39F010P-70 W39F010P-70 2138977A-A12 149OBSA st 1 line: winbond logo nd 2 line: the part number: W39F010P- line: the lot number th 4 line: the tracking code: 149 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ...etc. ...
Page 29
PACKAGE DIMENSIONS 13.1 32-pin P-DIP Notes Base Plane Seating Plane Publication Release Date: December 26, ...
Page 30
TSOP ( mm 0.10(0.004) b θ W39F010 Dimension in Inches Dimension in mm Symbol Min. Nom. Max. ...
Page 31
... E 13.4 32-pin STSOP ( mm θ Symbol Notes Dimensions D & not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches General appearance spec. should be based on final Publication Release Date: December 26, 2005 - 31 - W39F010 Dimension in Inches Dimension in mm Min. Nom. Max. Min. ...
Page 32
VERSION HISTORY VERSION DATE A1 Dec. 2000 A2 June 17, 2002 A3 April 15, 2005 December 26, A4 2005 PAGE - Initial Issued 1, 23 Add cycle of 1K Change active current from 10 to15mA (typ.) 1 Change standby ...
Page 33
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other ...