E28F400B5B60 Intel, E28F400B5B60 Datasheet
E28F400B5B60
Specifications of E28F400B5B60
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E28F400B5B60 Summary of contents
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... Based on Intel ® Boot Block architecture, the 5 Volt Boot Block Flash memory family enables quick and easy upgrades for designs that demand state-of-the-art technology. This family of products comes in industry- standard packages: the 40-lead TSOP for very space-constrained 8-bit applications, 48-lead TSOP, ideal for board-constrained higher-performance 16-bit applications, and the rugged, easy to handle 44-lead PSOP ...
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... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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INTRODUCTION..............................................5 1.1 Product Overview .........................................5 2.0 PRODUCT DESCRIPTION ..............................6 2.1 Pin Descriptions ...........................................6 2.2 Pinouts .........................................................8 2.3 Memory Blocking Organization...................10 2.3.1 One 16-KB Boot Block.........................10 2.3.2 Two 8-KB Parameter Blocks................10 2.3.3 Main Blocks - One 96-KB + Additional 128-KB ...
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... Added TE28F004B5 product offerings to ordering information chart. Added 55 ns speed capability for 2- and 4-Mbit devices. Revised I max value. CCD Name of document changed from Smart 5 Boot Block Flash Memory Family Mbit. -006 Added automotive temperature product offerings. -007 Modified document to show new 8-Mbit automotive temperature product offerings ...
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... As of the publication date of this document, not all 28F200B5 –60 devices meet the 55 ns read specification. Please refer to the 5 Volt Boot Block Flash Memory Family 28F200B5, 28F004/400B5, 28F800B5 Specification Update to determine the specific 28F200B5 –T/B60 material that is capable read access times. All other 28F200B5 T/B60 devic es are capable read access times when VCC = 5 V ± ...
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... SmartVoltage technology enables fast factory programming and low-power designs. Specifically designed for 5 V systems, 5 Volt Boot Block Flash components support read operations and internally configure to program/erase The option renders the fastest PP program and erase performance which will increase your factory throughput ...
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... Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched during the write cycle. Outputs array, intelligent identifier and status register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. ...
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... GND GROUND: For all internal circuitry CONNECT: Pin may be driven or left floating. 2.2 Pinouts Intel ® 5 Volt Boot Block Flash architecture provides upgrade paths in each package pinout up to the 8-Mbit density. The 44-lead PSOP pinout follows the industry-standard ROM/EPROM pinout, as shown in Figure 1. Designs with space concerns should consider the 48-lead pinout shown in Figure 2 ...
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WP# WP ...
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... EEPROM. By using software techniques, the byte-rewrite functionality of EEPROMs can be emulated. These techniques At are detailed in Intel’s application note, AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM . The parameter blocks are not write-protectable. 2.3.3 MAIN BLOCKS - ONE 96-KB + ...
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BOOT BLOCK 1E000H 3E000H 3DFFFH 1DFFFH 8-Kbyte PARAMETER BLOCK 1D000H 3D000H 3CFFFH 1CFFFH 8-Kbyte PARAMETER BLOCK 1C000H 3C000H 3BFFFH 1BFFFH 96-Kbyte MAIN BLOCK 10000H 30000H 2FFFFH 0FFFFH 128-Kbyte MAIN BLOCK 20000H 00000H 1FFFFH 10000H 0FFFFH 00000H ...
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BOOT BLOCK 7C000H 3C000H 7BFFFH 3BFFFH 8-Kbyte PARAMETER BLOCK 7A000H 3A000H 79FFFH 39FFFH 8-Kbyte PARAMETER BLOCK 78000H 38000H 77FFFH 37FFFH 96-Kbyte MAIN BLOCK 60000H 20000H 5FFFFH 1FFFFH 128-Kbyte MAIN BLOCK 40000H 00000H 3FFFFH ...
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... The local CPU reads and writes flash memory in- 9 system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. Four control pins dictate the data flow in and out of the component: CE#, OE#, WE#, and RP#. These bus operations are summarized in Tables 3 and 4. ...
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... CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
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... Table 3. Bus Operations for Word-Wide Mode (BYTE Mode Notes RP# Read 1,2 Output Disable V IH Standby V IH Deep Power-Down Intelligent Identifier (Mfr.) Intelligent Identifier 4 (Device) Write 6,7 Table 4. Bus Operations for Byte-Wide Mode (BYTE Mode Note RP# CE# OE# Read 1,2 Output Disable Standby ...
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... H NOTE: In byte-mode, the upper byte will be tri-stated. 16 3.2.2 READ IDENTIFIER To read the manufacturer and device codes, the device must be in intelligent identifier read mode, which can be reached using two methods: by writing the intelligent identifier command (90H taking the A pin identifier ...
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Issue the Clear Status Register command (50H) ...
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... Table 6. Command Codes and Descriptions Code Device Mode 00 Invalid/ Unassigned commands that should not be used. Intel reserves the right to redefine Reserved these codes for future functions. FF Read Array Places the device in read array mode, so that array data will be output on the data pins ...
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... SRD - Data read from Status Register. 4. IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and device codes Address within the block being erased Address to be programmed Data to be programmed at location PA. ...
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Table 8. Status Register Bit Definition WSMS ESS SR.7 WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS Erase Suspended 0 = Erase In Progress/Completed ...
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Start Write 40H, Word/Byte Address Write Word/Byte Data/Address Read Status Register NO SR YES Full Status Check if Desired Word/Byte Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range ...
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Start Write 20H, Block Address Write D0H and Block Address Read Status Register Suspend Erase Loop NO 0 YES Suspend SR.7 = Erase 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read ...
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Start Write B0H Write 70H Read Status Register 0 SR SR.6 = Erase Resumed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Array Data Erase Resumed Figure 10. Erase Suspend/Resume ...
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... The following section discusses recommended design considerations which can improve the robustness of system designs using flash memory. 4.1 Power Consumption Intel flash components contain features designed to reduce power requirements. The following sections will detail how to take advantage of these features. 4.1.1 ACTIVE POWER ...
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... If a CPU reset occurs without a flash memory reset, proper CPU initialization would not occur because the flash memory may in a mode other than Read Array. Intel’s Flash memories initialization following a system reset by connecting the RP# pin to the same RESET# signal that resets the system CPU ...
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... CC 26 NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the " ...
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Capacitance ° MHz A Symbol Parameter Note C Input Capacitance Output Capacitance 4, 7 OUT 1. Sampled, not 100% tested. 5.4 DC Characteristics—Commercial and Extended Temperature Temp Sym Parameter Note ...
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... PPES I RP# Unlock Current 1,4 RP Identifier Current 1 5.4 DC Characteristics—Commercial and Extended Temperature Temp Sym Parameter Note V A Intelligent Identifier 9 ID Voltage V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage Output High Voltage (TTL Output High Voltage (CMOS) ...
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NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at V product versions (packages and speeds specified with the device deselected. If the device is read while in erase suspend mode, current draw is ...
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DC Characteristics—Automotive Temperature Sym Parameter Notes I V Read Current for 1,5,6 CCR CC Word or Byte I V Program Current for 1,4 CCW CC Word or Byte I V Erase Current 1,4 CCE CC I ...
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... Erase Current 1 PPE Erase Suspend 1 PPES PP Current I RP# Boot Block Unlock 1,4 RP# Current I A Intelligent Identifier 1 Current V A Intelligent Identifier ID 9 Voltage V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL (TTL Output High Voltage OH (TTL Output High Voltage OH (CMOS) V ...
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NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at V product versions (packages and speeds specified with the device deselected. If the device is read while in erase suspend mode, ...
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DEVICE UNDER TEST NOTE: C includes jig capacitance. L Figure 13. Test Configuration Test Configuration Component Values Test Configuration C (pF Standard Test 100 ...
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... As of the publication date of this document, not all 28F200B5 –60 devices meet the 55 ns read specification. Please refer to the 5 Volt Boot Block Flash Memory Family 28F200B5, 28F004/400B5, 28F800B5 Specification Update to determine the specific 28F200B5 –T/B60 material that is capable read access times. All other 28F200B5 T/B60 devices are ...
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... As of the publication date of this document, not all 28F200B5 –60 devices meet the 55 ns read specification. Please refer to the 5 Volt Boot Block Flash Memory Family 28F200B5, 28F004/400B5, 28F800B5 Specification Update to determine the specific 28F200B5 –T/B60 material that is capable read access times. All other 28F200B5 T/B60 devices are ...
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... Typical conditions are 25 °C with V and 5 12.0 V typically results in a 60% reduction in programming time Contact your Intel representative for information regarding maximum byte/word write specifications. 5. Max program times are guaranteed for the two parameter blocks and 96-KB main block only. 36 Data Valid ...
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... 12.0 V typically results in a 60% reduction in programming time Contact your Intel representative for information regarding maximum byte/word write specifications. 5. Max program times are guaranteed for the two parameter blocks and 96-KB main block only. PRELIMINARY 28F200B5, 28F004/400B5, 28F800B5 5 V ± 10 ± ...
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AC Characteristics—Write Operations—Commercial and Extended Temperature # Sym RP# High Recovery to WE# (CE#) Going PHWL PHEL Low CE# (WE#) Setup to WE# (CE#) Going ELWL WLEL Low ...
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AC Characteristics—Write Operations—Automotive Temperature # Sym Parameter W0 t Write Cycle Time AVAV RP# High Recovery to WE# PHWL PHEL (CE#) Going Low CE# (WE#) Setup to WE# ELWL WLEL (CE#) ...
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ADDRESSES [ CE#(WE#) [E(W OE# [ WE#(CE#) [W(E High Z DATA [D/ ...
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... Voltage Options ( Architecture B = Boot Block 44-Lead PSOP 48-Lead TSOP PA28F200B5T60 E28F200B5T60 PA28F200B5B60 E28F200B5B60 PA28F200B5T80 E28F200B5T80 PA28F200B5B80 E28F200B5B80 PA28F400B5T60 E28F400B5T60 PA28F400B5B60 E28F400B5B60 PA28F400B5T80 E28F400B5T80 PA28F400B5B80 E28F400B5B80 PA28F800B5T70 E28F800B5T70 PA28F800B5B70 E28F800B5B70 PA28F800B5T90 E28F800B5T90 PA28F800B5B90 E28F800B5B90 TB28F200B5T80 TE28F200B5T80 TB28F200B5B80 TE28F200B5B80 TB28F400B5T80 TE28F400B5T80 TB28F400B5B80 TE28F400B5B80 TB28F800B5T90 ...
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... SmartVoltage Boot Block Flash Memory Family datasheet NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. ...
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WRITE STATE MACHINE: CURRENT-NEXT STATE CHART Current SR.7 Data Read Program State When Array Setup Read (FFH) (10/40H) Read Read Program Array “1” Array Array Setup Program Setup “1” Status Program: Not “0” Status Complete Program: Read Program Complete “1” ...
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PRODUCT BLOCK DIAGRAM 44 APPENDIX B PRELIMINARY 7769_01 ...