E28F400B5B60 Intel, E28F400B5B60 Datasheet - Page 38

• Manufacturer Part Number: E28F400B5B60
• Manufacturer: Intel

Specifications of E28F400B5B60

• Density: 4Mb
• Access Time (max): 60ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

28F200B5, 28F004/400B5, 28F800B5
5.10
NOTES:
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
3. Refer to command definition table for valid A
4. Refer to command definition table for valid D
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at V
7. Time t
8. Sampled, but not 100% tested.
9. Write pulse width (t
10. Write pulse width high (t
38
W10 t
W11 t
W12 t
W13 t
W14 t
W1
W2
W3
W4
W5
W6
W7
W8
W9
#
Characteristics—Read-Only Operations.
which includes verify operations.
successfully.
(whichever goes high first). Hence, t
(whichever goes low first). Hence, t
t
t
t
t
t
t
t
t
t
PHWL
ELWL
WP
DVWH
AVWH
WHEH
WHDX
WHAX
PHHWH
VPWH
QVPH
QVVL
PHBR
WPH
PHBR
AC Characteristics—Write Operations—Commercial and Extended
Temperature
is required for successful locking of the boot block.
(t
Sym
(t
(t
(t
(t
(t
(t
(t
WLEL
(t
PHEL
DVEH
AVEH
EHWH
EHDX
EHAX
VPEH
PHHEH
)
)
WP
)
)
)
)
)
)
) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
)
WPH
RP# High Recovery to WE# (CE#) Going
Low
CE# (WE#) Setup to WE# (CE#) Going
Low
Write Pulse Width
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
Write Pulse Width High
RP# V
V
RP# V
V
Boot Block Lock Delay
) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
PP
PP
Setup to WE# (CE#) Going High
Hold from Valid SRD
HH
HH
WPH
WP
Setup to WE# (CE#) Going High
Hold from Valid SRD
= t
= t
WLWH
WHWL
IN
IN
Parameter
. (Table 7)
. (Table 7)
= t
= t
ELEH
EHEL
HH
= t
= t
V
V
10%
WLEH
or WP# should be held at V
WHEL
CC
CC
= 5 V
= 5 V
= t
= t
ELWH
EHWL
.
.
5%
Note Min Max Min Max Unit
6,8
5,8
6,8
5,8
7,8
9
4
3
4
3
IH
450
100
100
until operation completes
50
50
50
10
20
0
0
0
0
0
0
Comm
PRELIMINARY
100
Extended
450
100
100
60
60
60
10
20
0
0
0
0
0
0
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns