MT48LC4M32B2F5-6 Micron Technology Inc, MT48LC4M32B2F5-6 Datasheet - Page 24

MT48LC4M32B2F5-6

Manufacturer Part Number
MT48LC4M32B2F5-6
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC4M32B2F5-6

Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
17/7.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
195mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC4M32B2F5-6:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48LC4M32B2F5-6:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48LC4M32B2F5-6AIT:L
Manufacturer:
MICRON
Quantity:
1 000
Figure 11:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
Random READ Accesses
Notes:
COMMAND
COMMAND
COMMAND
1. Each READ command may be to either bank. DQM is LOW.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
ADDRESS
ADDRESS
ADDRESS
CLK
CLK
CLK
DQ
DQ
DQ
BANK,
BANK,
T0
COL n
T0
COL n
T0
BANK,
COL n
READ
READ
READ
CL = 1
CL = 2
T1
T1
BANK,
BANK,
T1
READ
READ
READ
BANK,
COL a
COL a
COL a
D
OUT
n
CL = 3
T2
BANK,
T2
BANK,
T2
COL x
COL x
BANK,
READ
READ
READ
COL x
D
D
OUT
OUT
a
n
24
T3
T3
T3
BANK,
COL m
BANK,
COL m
READ
READ
BANK,
COL m
READ
D
D
D
OUT
OUT
OUT
x
a
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
T4
T4
NOP
NOP
NOP
D
D
D
OUT
m
OUT
OUT
x
a
T5
T5
NOP
NOP
D
D
OUT
m
OUT
x
DON’T CARE
T6
NOP
D
OUT
m
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition

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