CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 101

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 10-35. Latency of SRAM Write Cycle from Second Cycle of Learn Instruction
The Learn operation lasts two CLK cycles. The sequence of operation is as follows.
Document #: 38-02040 Rev. *F
• Cycle 1A: The host ASIC applies the Learn instruction on CMD[1:0] using CMDV = 1. The CMD[5:2] field specifies the index
• Cycle 1B: The host ASIC continues to drive the CMDV to 1, the CMD[1:0] to 11, and the CMD[5:2] with the comparand pair
of the comparand register pair that will be written in the data array in the 144-bit-configured table. For a Learn in a 72-bit-
configured table, the even-numbered comparand specified by this index will be written. CMD[8:6] carries the bits that will be
driven on SADR[23:21] in the SRAM Write cycle.
index. CMD[6] must be set to 0 if the Learn is being performed on a 72-bit-configured table, and to 1 if the Learn is being
performed on a 144-bit-configured table.
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
TLSZ = 01, LRAM = 1, LDEV = 1.
1 (TLSZ = 00)
SADR[23:0]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
CMDV
WE_L
OE_L
CE_L
SSV
SSF
Figure 10-75. Timing Diagram of Learn on Device Number 7 (TLSZ = 01)
DQ
z
z
1
1
0
0
0
Comp1
cycle
Learn1
1A 1B
1
X
cycle
2
X
X
X
X
cycle
Comp2
Learn2
3
X
cycle
4
X
X
X
X
cycle
5
z
cycle
Latency in CLK Cycles
1
6
cycle
z
7
z
z
cycle
4
5
6
8
1
1
cycle
z
9
z
z
cycle
10
z
1
1
0
CYNSE70128
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