CYNSE70128-83BGC Cypress Semiconductor Corp, CYNSE70128-83BGC Datasheet - Page 27

• Manufacturer Part Number: CYNSE70128-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70128-83BGC

• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The CYNSE70128 writes the data on the DQ[71:0] bus only to the subfield that has the corresponding mask bit set to 1 in the
GMR specified by the index {CMD[10],CMD[5:3]} supplied in cycle 1. The CYNSE70128 drives the EOT signal low from cycle 3
to cycle n; the CYNSE70128 drives the EOT signal high in cycle n + 1 (n is specified in the BLEN field of the WBURREG).
At the termination of cycle n + 2, the CYNSE70128 floats the EOT signal to a three-state operation, and a new instruction can
begin.
Table 10-9. Write Address Format for Data and Mask Array (Burst Write)
10.5
In order to write the data and mask arrays faster for initialization, testing, or diagnostics, many locations can be written simulta-
neously in the CYNSE70128 device using Parallel Write. Parallel Write allows the user to specify one address and write multiple
locations in the data or mask array with the same data.In order to perform Parallel Write, CMD[9] should be set in cycles A and
B of the Write command to the data or mask arrays. The address bits DQ[10:1] specify which location to perform parallel write
to. DQ[15:11] defines a set of 32 partitions all of which write two 72 bit entries (DQ[0] is ignored). Thus 64 72-bit locations are
simultaneously written in either the data or mask array during Parallel Write.
10.6
This subsection describes the following:
10.6.1
Figure 10-5 shows the timing diagram for a Search command in the 72-bit-configured table (CFG = 0000000000000000)
consisting of a single device for one set of parameters: TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1. The hardware diagram
for this search subsystem is shown in Figure 10-6.
Document #: 38-02040 Rev. *F
• Cycles 3 to n + 1: The host ASIC drives the DQ[71:0] with the data to be written to the next data or mask array location
• Cycle n + 2: TheCYNSE70128 drives the EOT signal LOW.
• 72-bit search on tables configured as ×72 using one device
• 72-bit search on tables configured as ×72 using up to eight devices
• 72-bit search on tables configured as ×72 using up to 31 devices
• 144-bit search on tables configured as ×144 using one device
• 144-bit search on tables configured as ×144 using up to eight devices
• 144-bit search on tables configured as ×144 using up to 31 devices
• 288-bit search on tables configured as ×288 using one device
• 288-bit search on tables configured as ×288 using up to eight devices
• 288-bit search on tables configured as ×288 using up to 31 devices
• Mixed-size searches on tables configured with different widths using an CYNSE70128 with CFG_L low
• Mixed-size searches on tables configured with different widths using an CYNSE70128 with CFG_L high.
DQ[71:26]
(addressed by the auto-increment ADR field of the WBURREG register) of the selected device.
Reserved
Reserved
Parallel Write
Search Command
72-bit Search on Tables Configured as ×72 Using a Single CYNSE70128 Device
DQ[25:21]
ID
ID
01: Mask array
00: Data array
DQ[20:19]
DQ[18:16]
Reserved
Reserved
Do not care
(WBURADR), which increments with each access.
Do not care
(WBURADR), which increments with each access.
. These 16 bits come from the internal register
. These 16 bits come from the internal register
DQ[15:0]
CYNSE70128
Page 27 of 137