MC145423DWR2 Freescale Semiconductor, MC145423DWR2 Datasheet - Page 12

• Manufacturer Part Number: MC145423DWR2
• Manufacturer: Freescale Semiconductor

Specifications of MC145423DWR2

• Number Of Transmitters: 1
• Power Supply Requirement: Single
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / Rohs Status: Not Compliant

MC145423
250 s have elapsed without a burst from the master
being successfully demodulated. This allows the slave
device to self power-up and power-down in demand
powered loop systems. When held low, the device
powers down and the only active circuitry, is that
which is necessary for the demodulation of data. When
held high, the device is powered up and transmits
normally in response to received bursts from the
master.
MOD TRI/SQ
Modulation Select (Pin 14)
modulation which has a slew controlled voltage output
for reduced EMI/RFI. This output looks like a triangle
waveform that is modulated with different angles for
the peaks. A logic high (V DD ) on this pin, selects
square wave output for maximum power to the line.
Tx
Transmit Data Output (Pin 15)
impedance when TE1 is low. When TE1 is high, this
pin presents new 8-bit B channel data on rising edges
of TDC-RDC.
on this pin on the rising edge of BCLK, while TE1 is
high. This pin is high impedance when TE1 is low.
impedance when both TE1 and TE2 are low. This pin
serves as an output for B channel information received
from the slave device. The B channel data is under
control of TE1 and TE2 and TDC-RDC.
the B channel data received from the master.
B channel 1 data is output on the first eight cycles of
the BCLK output when EN1 is high. B channel 2 data
is output on the next eight cycles of the BCLK, when
EN2 is high. B channel data bits are clocked out on the
rising edge of the BCLK output pin.
EN2-TE2/SIE/B1B2
B Channel 2 Enable Output or
Signal Insert Enable (Pin 16)
pin functions as SIE. When held high, this pin causes
signal bit 2, as received from the slave, to be inserted
into the LSB of the outgoing PCM word at the Tx pin.
The SDI2 pin will be ignored, and in its place, the LSB
22
A logic low (0 V) on this pin selects the MDPSK
Master Mode (UDLT-1): This pin is high
Slave Mode (UDLT-1): B channel data is output
Master Mode (UDLT-2): This pin is high
Slave Mode (UDLT-2): This pin is an output for
Master Mode (SIE UDLT-1): In this mode, this
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of the incoming word at the Rx pin will be transmitted
to the slave. The PCM word to the slave will have LSB
forced low in this mode. In this manner, signal bit 2 to/
from the slave UDLT is inserted into the PCM words
the master sends and receives from the backplane, for
routing through the PABX for simultaneous voice/data
communication. The state of this pin is internally
latched if the SE pin is brought and held low.
an input and selects the timeslot used for transferring
the receive data word. When this pin is low, the device
uses the RE1 pin timing the same as the MC145426
UDLT-1 slave. When this pin is a logic 1, the receive
word is latched in during the TE1 timeslot,
simultaneously with the transmit word transfer. The
RE1 pin timing is not affected by this selection.
this pin functions as EN2-TE2. This pin, along with
TE1 pin-17 control the output of data for their
respective B-channel on the Tx output pin. When both
TE1 and TE2 are low, the Tx pin is high impedance.
The rising edge of the respective enable produces the
first bit of the selected B-channel data on the Tx pin.
Internal circuitry then scans for the next negative
transition of the TDC-RDC clock. Following this
event, the next seven bits of the selected B-channel
data are output on the next seven rising edges of the
TDC-RDC data clock. When TE1 and TE2 are high
simultaneously, data on the Tx pin is undefined. TE1
and TE2 should be approximately leading-edge
aligned with the TDC-RDC data clock. To keep the Tx
pin out of the high impedance state, these enable lines
should be high while the respective B channel data is
being output.
EN2-TE2, this pin is an output and serves as an 8 kHz
enable signal for the input and output of the B channel
2 data. While EN2 is high, B channel 2 data is clocked
out on the Tx pin on the eight rising edges of the
BCLK. During this same time, B channel 2 input data
is clocked in on the Rx pin, on the eight falling edges
of the BCLK.
EN1-TE1
B Channel 1 Enable Output (Pin 17)
serves to control B channel 1 data. See the above pin
description for more information. EN1 serves as the
slave device’s 8 kHz frame reference signal. The VD
Slave Mode (UDLT-1): In this mode, this pin is
Master Mode (EN2-TE2 UDLT-2): In this mode,
Slave Mode (EN2-TE2 UDLT-2): Functioning as
This pin is the logical inverse of EN2-TE2, and
pin is also updated on the rising edge of the EN1
signal.
MSI/TONE
Master Sync Input or Tone Enable Input
(Pin 18)
frame reference input. The rising edge of MSI loads
B and D channel data, which had been input during the
previous frame, into the modulator section of the
device, and initiates the outbound burst onto the
twisted pair cable. The rising edge of MSI also
initiates the buffering of the B and D channel data
demodulated during the previous frame. MSI should
be approximately leading edge aligned with the TDC-
RDC data clock input signal.
500 Hz square wave PCM tone to be inserted in place
of the demodulated data. This feature allows the
designer to provide audio feedback for telset keyboard
depressions.
CCI/XTAL in
Convert Clock Input or Crystal Input (Pin 19)
clock signal should be applied to this pin. This signal
is used for internal sequencing and control. This signal
should be frequency and phase coherent with MSI for
optimum performance.
crystal is tied between this pin and XTAL out (pin 20).
A 10 M resistor across this pin and XTAL out and
25 pF capacitors from this pin and XTAL out to V SS
are required for stability and to ensure start-up. This
pin may be driven from an external source. XTAL out
should be left open if an external signal is used on this
input.
clock should be supplied to this input. The 8.192 MHz
input should be 50% duty cycle. This signal may free
run with respect to all other clocks without
performance degradation.
8.192 MHz crystal is tied between this pin and the
XTAL out (pin 20). A 10 M resistor between
XTAL in and XTAL out and 25 pF capacitors from
XTAL in and XTAL out to V SS are required to ensure
stability and start-up. XTAL in may also be driven with
an external 8.192 MHz signal if a crystal is not
Master Mode (MSI): This pin is the master 8 kHz
Slave Mode (TONE): A high on this pin causes a
Master Mode (CCI UDLT-1): A 2.048 MHz
Slave Mode (XTAL in UDLT-1): A 4.096 MHz
Master Mode (CCI UDLT-2): An 8.192 MHz
Slave Mode (XTAL in UDLT-2): Normally, an
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