MC145423DWR2 Freescale Semiconductor, MC145423DWR2 Datasheet - Page 9

• Manufacturer Part Number: MC145423DWR2
• Manufacturer: Freescale Semiconductor

Specifications of MC145423DWR2

• Number Of Transmitters: 1
• Power Supply Requirement: Single
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / Rohs Status: Not Compliant

MC145423
V SS
Negative Supply (Pin 1)
tied to system ground (0 V).
V ref
Voltage Reference Output (Pin 2)
(mid-supply) and should be bypassed to both V SS and
V DD with 0.1 F capacitors. This pin usually serves
as an analog ground reference for transformer
coupling of the device’s incoming bursts from the line.
No external load should be placed on this pin.
LI
Line Input (Pin 3)
incoming bursts. This input has an internal 240 k
resistor tied to the V ref pin, so an external capacitor or
line transformer may be used to couple the input signal
to the device with no dc offset.
LB
Loopback Low Input (Pin 4)
modulator output to the internal demodulator input,
which loops the entire burst for testing purposes.
During the loopback operation, the LI input is ignored,
and the LO1 and LO2 outputs are driven to equal
voltages. The state of the LB pin is internally latched if
the SE pin is held low. This feature is only active when
the PD input is high.
the incoming B channels from the master are burst
back to the master, instead of the Rx B channel input
data. The SDI1 and SDI2 functions operate normally
in this mode, and the BCLK (pin 23) is held low.
Additionally, for both the UDLT-1 and UDLT-2 mode,
when the TONE (pin 18) and loopback functions are
active simultaneously, the loopback function overrides
the TONE function.
VD
Valid Data Output (Pin 5)
transmission has been demodulated. A valid line
transmission burst is determined by proper
20
This is the most negative power pin, and should be
This is the output from the internal reference supply
This pin is the input to the demodulator for the
Master Mode: A low on this pin ties the internal
Slave Mode: When this pin is low and PD is high,
A high level on this pin indicates that a valid line
PIN DESCRIPTIONS
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
TELECOMMUNICATIONS
synchronization and the absence of detected bit errors.
VD is a CMOS output and is high impedance when SE
is low.
edge of MSI, when PD is high. When PD is low, VD
changes state at the end of demodulation of a
transmission burst and does not change again until
three MSI rising edges have occurred, at which time it
goes low, or until the next demodulation of a burst.
have been received within the last 250 s, as
determined by an internal oscillator, VD will go low.
SDI1 and SDI2
D Channel Signaling Data Bit Inputs 1 and 2
(Pins 6 and 7)
8 kbps serial data inputs in UDLT-1 mode. Data on
these pins is loaded on the rising edge of MSI for
transmission to the slave. The state of these pins is
latched if SE is held low.
8 kbps serial data inputs in UDLT-1 mode. Data on
these pins is loaded on the rising edge of TE1 for
transmission to the master. If no transmissions from
the master are being received and PD is high, data on
these pins will be loaded into the part on an internal
signal. Therefore, data on these pins should be steady
until synchronous communication with the master has
been established, as indicated by the high on VD.
16 kbps serial data inputs in UDLT-2 mode. Two bits
should be clocked into each of these inputs between
the rising edges of the MSI frame reference clock. The
first bit of each D channel is clocked into an
intermediate buffer on the first falling edge of the
SDCLK following the rising edge of MSI. The second
bit of each D channel is clocked in on the next
negative transition of the SDCLK. If further SDCLK
negative edges occur, new information is serially
clocked into the buffer replacing the previous data,
one bit at a time. Buffered D channel bits are burst to
the slave on the next rising edge of the MSI frame
reference clock. The state of these pins is latched if SE
is held low.
16 kbps serial data inputs in UDLT-2 mode. The D
channel data bits are clocked in serially on the
negative edge of the 16 kbps SDCLK output pin.
Master Mode: VD changes state on the rising
Slave Mode: If no transmissions from the master
Master Mode (UDLT-1): These inputs are the
Slave Mode (UDLT-1): These inputs are the
Master Mode (UDLT-2): These inputs are the
Slave Mode (UDLT-2): These inputs are the
MC145423 UDLT-3 PIN STATES FOR UDLT-1 MAS
MC145423 UDLT-3 PIN STATES FOR UDLT-2 SLAV
Pin
No.
Pin
No.
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
FRAME
SDCLK
MC145423
MSI/TONE
TDC-RDC/
Name
2.048 MHz
MASTER/
10/20
SDI1
SDI2
EN1-TE1
LI SENS/
CLKOUT
V SS
XTAL out
V ref
Pin
VD
XTAL in
SLAVE
LB
MC145423
LI
Name
BCLK
RE1/
RE2/
CCI/
V DD
LO2
LO1
Pin
Rx
Analog
Output
Output
Power
In/out
Input
Input
Input
Input
Input
Ref
Don’t Care High Impedance High Imp
Output
Output
Power
In/out
Input
Input
Input
Input
Input
Input
Input
Input
Power Supply
Digital Out
Analog In
16 kbps
16 kbps
Normal
Data In
Data In
16 kHz
V DD /2
AGND
UDLT-2 Slave Mode
64 kbps Data In 64 kbps
CCI 2.048 MHz
Gnd
Modulator Out
Modulator Out
LI Sensitivity
1
1
TE1 8 kHz
MSI 8 kHz
RE1 8 kHz
TDC-RDC
Data Clk
Digital In
Powered-Up
Normal
+V
0
Power Supply
TELECOMMU
Digital Out
Analog In
LB Low
16 kbps
16 kbps
Data In
Data In
16 kHz
V DD /2
UDLT-1 Ma
AGND
Gnd
0
1
CCI 2.04
Power
LI Sen
LO2 =
LO1 =
RE1 8
TE1 8
MSI 8
TDC-
Digit
Data
LB L
+V
0