GS8640Z36GT-200V GSI TECHNOLOGY, GS8640Z36GT-200V Datasheet

GS8640Z36GT-200V

Manufacturer Part Number

GS8640Z36GT-200V

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS8640Z36GT-200V.pdf (22 pages)

Specifications of GS8640Z36GT-200V

Density

72Mb

Access Time (max)

7.5ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

133.3MHz

Operating Supply Voltage (typ)

1.8/2.5V

Address Bus

21b

Package Type

TQFP

Operating Temp Range

0C to 70C

Number Of Ports

Supply Current

230mA

Operating Supply Voltage (min)

1.7/2.3V

Operating Supply Voltage (max)

2/2.7V

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

100

Word Size

36b

Number Of Words

Lead Free Status / Rohs Status

Compliant

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• NBT (No Bus Turn Around) functionality allows zero wait

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• User-configurable Pipeline and Flow Through mode

• LBO pin for Linear or Interleave Burst mode

• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• ZZ Pin for automatic power-down

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

The GS8640Z18/36T-xxxV is a 72Mbit Synchronous Static

SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or

other pipelined read/double late write or flow through read/

single late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Rev: 1.03b 2/2009

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

read-write-read bus utilization; Fully pin-compatible with

both pipelined and flow through NtRAM™, NoBL™ and

ZBT™ SRAMs

Flow Through

Pipeline

3-1-1-1

2-1-1-1

72Mb Pipelined and Flow Through

Synchronous NBT SRAM

Curr

tCycle

Parameter Synopsis

(x32/x36)

(x18)

1/22

-250

340

410

245

280

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS8640Z18/36T-xxxV may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, meaning that in addition to the

rising edge triggered registers that capture input signals, the

device incorporates a rising-edge-triggered output register. For

read cycles, pipelined SRAM output data is temporarily stored

by the edge triggered output register during the access cycle

and then released to the output drivers at the next rising edge of

clock.

The GS8640Z18/36T-xxxV is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

standard 100-pin TQFP package.

3.0

4.0

6.5

-200

290

350

220

250

3.0

5.0

7.5

-167

260

305

210

240

3.4

6.0

8.0

Unit

GS8640Z18/36T-xxxV

250 MHz–167 MHz

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Related parts for GS8640Z36GT-200V

GS8640Z36GT-200V Summary of contents

Page 1

... Curr 410 350 (x32/x36) t 6.5 7.5 KQ 6.5 7.5 tCycle Curr 245 220 (x18) Curr 280 250 (x32/x36) 1/22 GS8640Z18/36T-xxxV 250 MHz–167 MHz 2.5 V I/O -167 Unit 3.4 ns 6.0 ns 260 mA 305 mA 8.0 ns 8.0 ns 210 mA 240 mA © 2004, GSI Technology DD ...

Page 2

... Pins marked with NC can be tied to either V Rev: 1.03b 2/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8640Z18T-xxxV Pinout (Package Top View These pins can also be left floating 2/22 GS8640Z18/36T-xxxV DDQ DQP DDQ DDQ DDQ © 2004, GSI Technology ...

Page 3

... Pins marked with NC can be tied to either V Rev: 1.03b 2/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8640Z36T-xxxV Pinout (Package Top View These pins can also be left floating 3/22 GS8640Z18/36T-xxxV DQP DDQ DDQ DDQ DDQ DQP 51 A © 2004, GSI Technology ...

Page 4

... Byte D Data Input and Output pins Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low Core power supply Ground Output driver power supply No Connect 4/22 GS8640Z18/36T-xxxV ; active low A9 ; active low B9 ; active low C9 ; active low D9 © 2004, GSI Technology ...

Page 5

... GS8640Z18/36T-xxxV NBT SRAM Functional Block Diagram Rev: 1.03b 2/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Amps Sense Drivers Write 5/22 GS8640Z18/36T-xxxV © 2004, GSI Technology ...

Page 6

... Rev: 1.03b 2/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com & determine which bytes will be written. All or none may be activated. A write C, D 6/22 GS8640Z18/36T-xxxV , E and E ). Deassertion of any one of the Enable © 2004, GSI Technology ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. External L Next L External L Next L External L None L Next L Next L None L None L None L None L None Current L 7/22 GS8640Z18/36T-xxxV High High High High-Z 1,2,3, High High High High High © 2004, GSI Technology Notes 1,10 2 1,2, 1,3, ...

Page 8

... and D represent input command codes ,as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipeline and Flow Through Read/Write Control State Diagram 8/22 GS8640Z18/36T-xxxV New Write Burst Write B D n+3 ƒ ƒ © 2004, GSI Technology ...

Page 9

... and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 9/22 GS8640Z18/36T-xxxV Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2004, GSI Technology ...

Page 10

... Pipeline and Flow Through Read Write Control State Diagram 10/22 GS8640Z18/36T-xxxV R B Data Out W (Q Valid) D Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 2004, GSI Technology ...

Page 11

... Note: The burst counter wraps to initial state on the 5th clock. 11/22 GS8640Z18/36T-xxxV Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2004, GSI Technology ...

Page 12

... Rev: 1.03b 2/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH DD 12/22 GS8640Z18/36T-xxxV 2. The duration of SB tZZR pipelined parts and V on flow DDQ SS © 2004, GSI Technology ...

Page 13

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 13/22 GS8640Z18/36T-xxxV Value –0.5 to 4.6 –0 –0 +0.5 ( 4.6 V max.) DDQ –0 +0.5 ( 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 1.8 2.0 V 2 © 2004, GSI Technology Unit Notes ...

Page 14

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn Overshoot Measurement and Timing Symbol Test conditions I/O OUT 14/22 GS8640Z18/36T-xxxV Typ. Max. Unit V + 0.3 V — DD 0.3*V V — DD Typ. Max. Unit   20% tKC DD IL Typ. Max. Unit © 2004, GSI Technology Notes 1 1 Notes 2 2 ...

Page 15

... OL2 OL 15/22 GS8640Z18/36T-xxxV Figure 1 Output Load 1 * 50 30pF V DDQ/2 * Distributed Test Jig Capacitance Min –  –100 –1 uA OUT DD Min = 1 – 0.4 V DDQ DDQ = 2.375 V 1.7 V — — © 2004, GSI Technology Max 1 uA 100 Max — — 0.4 V 0.4 V ...

Page 16

... GSI Technology Unit ...

Page 17

... GSI Technology ...

Page 18

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Suspend Read C Write D Write No-op tKH tKH tKC tKC tKL tKL D(A) Q(B) Q(C) 18/22 GS8640Z18/36T-xxxV Read E Deselect E tLZ tHZ tKQ tKQX D(D) Q(E) © 2004, GSI Technology ...

Page 19

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Write B+1 Read C Cont tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 19/22 GS8640Z18/36T-xxxV Read D Write E Read F Write tKQ tKQX tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE © 2004, GSI Technology tKQX D(G) ...

Page 20

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. TQFP Package Drawing (Package T)  0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 7 — 20/22 GS8640Z18/36T-xxxV E1 E © 2004, GSI Technology ...

Page 21

... GS8640Z18T-200IV GS8640Z18T-167IV GS8640Z36T-250IV GS8640Z36T-200IV GS8640Z36T-167IV GS8640Z18GT-250V GS8640Z18GT-200V GS8640Z18GT-167V GS8640Z36GT-250V GS8640Z36GT-200V GS8640Z36GT-167V GS8640Z18GT-250IV GS8640Z18GT-200IV GS8640Z18GT-167IV GS8640Z36GT-250IV GS8640Z36GT-200IV GS8640Z36GT-167IV Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640Z36T-167IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 22

... Content • Added note to TQFP pinouts (pg • Updated Synchronous Truth Table (pg. 7); Removed Status column from Ordering Information table Content • (Rev1.03a: Corrected erroneous timing diagrams) • Rev1.03b: Removed “Preliminary” banner due to MP status 22/22 GS8640Z18/36T-xxxV © 2004, GSI Technology ...

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