S29AL016D90TFI02 Spansion Inc., S29AL016D90TFI02 Datasheet
S29AL016D90TFI02
Specifications of S29AL016D90TFI02
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S29AL016D90TFI02 Summary of contents
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... S29AL016D 16 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory Data Sheet This product has been retired and is not recommended for designs. For new and current designs, S29AL016J supercedes S29AL016D. This is the factory-recommended migration path. Please refer to the S29AL016J data sheet for specifications and ordering information. ...
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... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...
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... Reduces overall programming time when issuing multiple program command sequences Top or Bottom Boot Block Configurations Available Compatibility with JEDEC standards – Pinout and software compatible with single-power supply Flash – Superior inadvertent write protection Performance Characteristics High Performance – Access times as fast – ...
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... General Description The S29AL016D Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in- system with the standard system 3 ...
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... RESET#: Hardware Reset Pin 7.8 Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.9 Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.10 Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11 Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8. Common Flash Memory Interface (CFI 8.1 Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9. Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.1 Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.3 Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 ...
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Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figures Figure 7.1 Temporary Sector Unprotect Operation ...
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Tables Table 7.1 S29AL016D Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Product Selector Guide Speed Option Max access time ACC Max CE# access time Max OE# access time Note See AC Characteristics on page 40 2. Block Diagram RY/BY RESET# ...
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Connection Diagrams A15 1 A14 2 A13 3 A12 4 A11 5 6 A10 A19 WE# 11 RESET RY/BY# 15 A18 16 A17 ...
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... Special Handling Instructions Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. ...
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Pin Configuration A0–A19 DQ0–DQ14 DQ15/A-1 BYTE# CE# OE# WE# RESET# RY/BY Logic Symbol addresses 15 data inputs/outputs DQ15 (data input/output, word mode), ...
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... B = Fine-pitch Ball-Grid Array Package M = Small Outline Package (SOP) Standard Pinout Speed Option Access Speed Access Speed Device Number/Description S29AL016D 16 Megabit Flash Memory manufactured using 200 nm process technology 3.0 Volt-only Read, Program, and Erase S29AL016D Valid Combinations Package Type, Material, and Model Temperature Range ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of ...
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Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to V control and selects the device. OE# is the output control and gates array data to the ...
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... CMOS standby current (I will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t system can thus monitor RY/BY# to determine whether the reset operation is complete ...
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Output Disable Mode When the OE# input impedance state. Sector A19 A18 SA0 0 0 SA1 0 0 SA2 0 0 SA3 0 0 SA4 0 0 SA5 0 0 SA6 0 0 SA7 0 0 ...
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Sector A19 A18 SA0 0 0 SA1 0 0 SA2 0 0 SA3 0 0 SA4 0 0 SA5 0 0 SA6 0 0 SA7 0 0 SA8 0 0 SA9 0 0 SA10 0 0 SA11 0 1 SA12 ...
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... The alternate method intended only for programming equipment requires V This method is compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices. Details on this method are provided in a supplement, publication number 21468. Contact a Spansion representative to request a copy ...
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Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V sectors can be programmed or erased by selecting the sector ...
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Figure 7.2 In-System Sector Protect/Unprotect Algorithms START PLSCNT = 1 RESET Wait 1 μs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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... Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data ...
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... February 27, 2009 S29AL016D_00_A8 Table 8.3 Device Geometry Definition Data N 4Eh 0015h Device Size = 2 50h 0002h Flash Device Interface description (refer to CFI publication 100) 52h 0000h 54h 0000h Max. number of byte in multi-byte write = 2 56h 0000h (00h = not supported) 58h 0004h Number of Erase Block Regions within device ...
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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system ...
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Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 10.1 on page 30 address and data values or writing them in the improper sequence resets the device to reading array ...
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Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, ...
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Note See Table 10.1 on page 30 9.6 Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock ...
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Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the ...
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The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. ...
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Command Definitions Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 Bottom Boot Block Byte Word Sector Protect Verify ...
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Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 11.1 on page 35 RY/BY#, and DQ6 each offer a method for determining whether a ...
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Notes Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be ...
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DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at ...
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Reading Toggle Bits DQ6/DQ2 Refer to Figure 11.2 on page 34 toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store ...
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DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle ...
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Absolute Maximum Ratings Storage Temperature Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground V (Note 1) CC A9, OE#, and RESET# All other pins (Note 1) Output Short Circuit Current Notes 1. Minimum DC voltage ...
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DC Characteristics 14.1 CMOS Compatible Parameter I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I CC2 ...
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... Zero Power Flash Figure 14 500 Note Addresses are switching at 1 MHz Note ° Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 1000 1500 2000 Time in ns Figure 14.2 Typical I CC1 2 3 Frequency in MHz S29AL016D 2500 3000 3500 vs. Frequency 3 ...
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Test Conditions Note Diodes are IN3064 or equivalent. Output Load Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 16. Key to Switching ...
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AC Characteristics 17.1 Read Operations Parameter JEDEC Std t t AVAV AVQV ACC t t ELQV GLQV EHQZ GHQZ DF t SR/W t OEH t t AXQX ...
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Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms READY Read or Write RESET# Pin Low (NOT During Embedded Algorithms READY Read or Write t RESET# Pulse Width RP t RESET# High ...
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CE# OE# BYTE# BYTE# DQ0–DQ14 Switching from word to byte mode DQ15/A-1 BYTE# BYTE# Switching from byte to DQ0–DQ14 word mode DQ15/A-1 CE# WE# BYTE# Note Refer to the Erase/Program Operations table for ...
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Erase/Program Operations Parameter JEDEC Std t t AVAV AVWL WLAX DVWH WHDX DH t OES t t GHWL GHWL t t ELWL WHEH CH ...
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Addresses CE# OE# WE# Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address for reading status data (see 2. Illustration shows device in word mode. Addresses CE# OE# WE# Data ...
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Addresses CE OE# WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Addresses CE# t OE# WE# DQ6/DQ2 t ...
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Figure 17.10 DQ2 vs. DQ6 for Erase and Erase Suspend Operations Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read ...
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RESET# SA, A6, A1, A0 Data CE# WE# OE# Note For sector protect For sector unprotect 17.6 Alternate ...
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Addresses WE# OE# CE# Data RESET# RY/BY# Notes program address program data, DQ7# = complement of the data written to the device Figure indicates the last two bus cycles of the command sequence. ...
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TSOP, SO, and BGA Pin Capacitance Parameter Symbol OUT C IN2 Notes 1. Sampled, not 100% tested. 2. Test conditions T = 25° 1.0 MHz. A February 27, 2009 S29AL016D_00_A8 ...
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Physical Dimensions 20.1 TS 048—48-Pin Standard TSOP STANDARD PIN OUT (TOP VIEW SEE DETAIL 0.25 2X (N/2 TIPS) PARALLEL TO SEATING PLANE Jedec MO-142 (D) DD Symbol MIN NOM A A1 0.05 A2 ...
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VBK048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8. 6.15 mm INDEX MARK PIN A1 CORNER PACKAGE VBK 048 JEDEC 8. 6.15 mm NOM PACKAGE SYMBOL MIN A --- A1 0.18 A2 0.62 D ...
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SO044—44-Pin Small Outline Package (SOP) 28. 13. S29AL016D S29AL016D_00_A8 February 27, 2009 Dwg rev AC; 10/99 ...
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Revision Summary 21.1 Revision A (May 4, 2004) Initial Release. 21.2 Revision A1 (July 28, 2004) Ordering Information Updated ordering information: model number, speed options, and valid combinations for TSOP and BGA packages. DC Characteristics Updated Max information for ...
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Revision A4 (June 17, 2005) Ordering Information Changed packing type from “1, 3” to “0, 1, 3” 21.6 Revision A5 (May 22, 2006) AC Characteristics Added t parameter to read and erase/program operations tables. Added back-to-back read/write cycle SR/W ...
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... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2004-2009 Spansion Inc. All rights reserved. Spansion ™ ™ ...