71V2558S133PF

Manufacturer Part Number71V2558S133PF
ManufacturerIDT, Integrated Device Technology Inc
71V2558S133PF datasheet
 


Specifications of 71V2558S133PF

Density4.5MbAccess Time (max)4.2ns
Sync/asyncSynchronousArchitectureSDR
Clock Freq (max)133MHzOperating Supply Voltage (typ)3.3V
Address Bus18bPackage TypeTQFP
Operating Temp Range0C to 70CNumber Of Ports1
Supply Current300mAOperating Supply Voltage (min)3.135V
Operating Supply Voltage (max)3.465VOperating Temperature ClassificationCommercial
MountingSurface MountPin Count100
Word Size18bNumber Of Words256K
Lead Free Status / Rohs StatusNot Compliant  
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Features
◆ ◆ ◆ ◆ ◆
128K x 36, 256K x 18 memory configurations
◆ ◆ ◆ ◆ ◆
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
◆ ◆ ◆ ◆ ◆
TM
ZBT
Feature - No dead cycles between write and read
cycles
◆ ◆ ◆ ◆ ◆
Internally synchronized output buffer enable eliminates the
need to control OE
◆ ◆ ◆ ◆ ◆
Single R/W W W W W (READ/WRITE) control pin
◆ ◆ ◆ ◆ ◆
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆ ◆ ◆ ◆ ◆
4-word burst capability (interleaved or linear)
◆ ◆ ◆ ◆ ◆
Individual byte write (BW
- BW
) control (May tie active)
1
4
◆ ◆ ◆ ◆ ◆
Three chip enables for simple depth expansion
◆ ◆ ◆ ◆ ◆
3.3V power supply (±5%), 2.5V I/O Supply (V
◆ ◆ ◆ ◆ ◆
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
complaint)
◆ ◆ ◆ ◆ ◆
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Description
The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBT
Turnaround.
Address and control signals are applied to the SRAM during one clock
Pin Description Summary
A
-A
Address Inputs
0
17
Chip Enables
CE
, CE
, CE
1
2
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
, BW
, BW
, BW
BW
1
2
3
4
CLK
Clock
ADV/LD
Advance burst address / Load new address
Linear / Interleaved Burst Order
LBO
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock
TDO
Test Data Output
JTAG Reset (Optional)
TRST
ZZ
Sleep Mode
I/O
-I/O
, I/O
-I/O
Data Input / Output
0
31
P1
P4
V
, V
Core Power, I/O Power
DD
DDQ
V
Ground
SS
©2007 Integrated Device Technology, Inc.
128K x 36, 256K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2556/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V2556/58 to
be suspended as long as necessary. All synchronous inputs are ignored
when (CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (CE
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
DDQ)
initiated.
The IDT71V2556/58 has an on-chip burst counter. In the burst mode,
the IDT71V2556/58 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. The LBO pin selects between linear and interleaved burst
sequence. The ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2556/58 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
, or Zero Bus
TM
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
1
IDT71V2556S/XS
IDT71V2558S/XS
IDT71V2556SA/XSA
IDT71V2558SA/XSA
, CE
, CE
) that allow the user
1
2
2
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Synchronous
Synchronous
Static
Static
4875 tbl 01
OCTOBER 2008
DSC-4875/09

71V2558S133PF Summary of contents

  • Page 1

    ... The IDT71V2556/58 has an on-chip burst counter. In the burst mode, the IDT71V2556/58 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence ...

  • Page 2

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs (1) Pin Definitions Symbol Pin Function I Address Inputs ADV/LD Advance / Load I R/W Read / Write I Clock Enable I CEN Individual Byte I - Write Enables Chip Enables ...

  • Page 3

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Functional Block Diagram LBO Address A [0:16] CE1, CE2, CE2 R/W CEN ADV/LD BWx Clock OE TMS TDI TCK TRST (optional Address D Q Control ...

  • Page 4

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Functional Block Diagram LBO Address A [0:17] CE1, CE2, CE2 R/W CEN ADV/LD BWx Clock OE TMS TDI TCK TRST (optional) Recommended DC Operating Conditions ...

  • Page 5

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Recommended Operating Temperature and Supply Voltage Grade Temperature V (1) SS Commercial 0°C to +70°C 0V Industrial -40°C to +85°C 0V NOTES the "instant on" case temperature. ...

  • Page 6

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Pin Configuration — 256K x 18 100 DDQ I I DDQ DDQ DDQ Top View TQFP NOTES: 1. Pins 14, 16 and 66 do not have to be connected directly the input voltage is ≥ ...

  • Page 7

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Pin Configuration — 128K x 36, 119 BGA DDQ I I DDQ I I DDQ K I DDQ DDQ Pin Configuration — 256K x 18, 119 BGA ...

  • Page 8

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Pin Configuration — 128K x 36, 165 fBGA (2) CE1 I I/O I I/O I I/O I I/O I (1) ( I/O I I/O I I/O I I LBO (2) Pin Configuration — 256K x 18, 165 fBGA ...

  • Page 9

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Synchronous Truth Table (5) CEN R/W Chip ADV/LD Enable L L Select Select Deselect NOTES Don’t Care When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle ...

  • Page 10

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Interleaved Burst Sequence Table First Address Second Address Third Address (1) Fourth Address NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. ...

  • Page 11

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Device Operation - Showint Mixed Load, Burst, Deselect and NOOP Cycles Cycle Address R/W ADV n+15 ...

  • Page 12

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Burst Read Operation Cycle Address R/W ADV NOTES High Low Don’t Care High Impedance defined and (1) Write Operation ...

  • Page 13

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Read Operation with Clock Enable Used Cycle Address R/W ADV NOTES High Low Don’t Care High Impedance defined as CE ...

  • Page 14

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Read Operation with Chip Enable Used Cycle Address R/W ADV NOTES High Low Don’t Care Don’t Know High Impedance. ...

  • Page 15

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter |I | Input Leakage Current LBO, JTAG and ZZ Input Leakage Current Output Leakage Current ...

  • Page 16

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs AC Electrical Characteristics (V = 3.3V±5%, Commercial and Industrial Temperature Ranges) DD Symbol Parameter t Clock Cycle Time CYC (1) Clock Frequence t F (2) Clock High Pulse Width ...

  • Page 17

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of Read Cycle Commercial and Industrial Temperature Ranges (1,2,3,4) 6. ...

  • Page 18

    ... Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM ...

  • Page 19

    ... Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM represents the input data to the SRAM corresponding to address signals ...

  • Page 20

    ... CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. ...

  • Page 21

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of CS Operation Commercial and Industrial Temperature Ranges (1,2,3,4) 6. ...

  • Page 22

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs JTAG Interface Specification (SA Version only TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO ( 3) TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. ...

  • Page 23

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs JTAG Identification Register Definitions (SA Version only) Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) Available JTAG Instructions ...

  • Page 24

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs 100 Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline Commercial and Industrial Temperature Ranges 6.42 24 ...

  • Page 25

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs 119 Ball Grid Array (BGA) Package Diagram Outline Commercial and Industrial Temperature Ranges 6.42 25 ...

  • Page 26

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs 165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline Commercial and Industrial Temperature Ranges 6.42 26 ...

  • Page 27

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of OE Operation OE DATA OUT NOTE read operation is assumed progress. Ordering Information XXXX Device Power Speed Type (1) t OHZ XX X Package ...

  • Page 28

    ... IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Datasheet Document History 6/30/99 8/23/99 Pp Pg. 6 Pg. 14 Pg. 15 Pg. 22 Pg. 24 10/4/99 Pg. 14 Pg. 15 12/31/99 04/30/00 Pg. 5,6 Pg. 6 Pg. 7 Pg. 21 05/26/00 Pg. 23 07/26/00 Pg ...