N80C251SB16 Intel, N80C251SB16 Datasheet - Page 31

• Manufacturer Part Number: N80C251SB16
• Manufacturer: Intel

Specifications of N80C251SB16

• Cpu Family: MCS251
• Device Core Size: 8b
• Frequency (max): 16MHz
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Factory-programmed ROM, OTPROM and EPROM versions of 8XC251SA/SB/SP/SQ use configura-
tion byte information supplied in a separate hexadecimal disk file. 8XC251SA/SB/SP/SQ devices
without internal ROM/OTPROM/EPROM arrays fetch configuration byte information from external
application memory based on an internal address range of FF:FFF9:8H.
UCONFIG0
7
Number
UCON
Bit
6:5
3:2
7
4
1
0
WSA1#
Mnemonic
(see Note)
RD1, RD0
WSA1#,
WSA0#
PAGE#
XALE#
UCON
SRC
Bit
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
WSA0#
Configuration byte location selector:
Clearing this bit causes the device to fetch configuration information
from on-chip memory. Setting this bit causes the device to locate
configuration information based upon the state of EA# during reset
(EA# = V
Wait State Select (for all pages except 01H). WSA0# is identical to
the WSA bit defined in the 8XC251SB A-step:
WSA1#WSA0# Description
Extend Ale:
If this bit is set, the time of the ALE pulse is T
extends the time of the ALE pulse from T
one external wait state.
RD# and PSEN# function select:
RD1RD0RD# RangeP1.7/CEX4/A17 PSEN# Range
Page Mode Select:
Clear this bit for page-mode (A15:8/D7:0 on P2, and A7:0 on P0).
Set this bit for nonpage-mode (A15:8 on P2, and A7:0/D7:0 on P0
(compatible with MCS 51 microcontrollers)).
Source Mode/Binary Mode Select:
Set this bit for source mode. Clear this bit for binary mode (binary-
code compatible with MCS 51 microcontrollers).
1
1
0
0
0 0 RD# = A16A17onlyAll Addresses
0 1 RD# = A16P1.7/CEX4All Addresses
1 0 P3.7 onlyP1.7/CEX4All Addresses
1 1 ≤ 7F:FFFFHP1.7/CEX4≥ 80:0000H
Figure 17. Configuration Byte 0
XALE#
1
0
1
0
CC
= on-chip; EA# = V
No wait states (01: page controlled by CONFIG1)
Insert 1 wait state for all pages except the 01: page
Insert 2 wait states for all pages except the 01: page
Insert 3 wait states for all pages except the 01: page
NOTE:
RD1
Function
SS
= off-chip).
RD0
OSC
to 3T
OSC
PAGE#
Address FF:FFF8H
. Clearing this bit
OSC
,
which adds
SRC
0
31