AM29F010-45PC Spansion Inc., AM29F010-45PC Datasheet - Page 2

• Manufacturer Part Number: AM29F010-45PC
• Manufacturer: Spansion Inc.

Specifications of AM29F010-45PC

• Cell Type: NOR
• Density: 1Mb
• Access Time (max): 45ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 17b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PDIP
• Program/erase Volt (typ): 4.75 to 5.25V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Word Size: 8b
• Number Of Words: 128K
• Supply Current: 30mA
• Mounting: Through Hole
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

GENERAL DESCRIPTION
The Am29F010 is a 1 Mbit, 5.0 Volt-only Flash memory
organized as 131,072 bytes. The Am29F010 is offered
in 32-pin PLCC, TSOP, and PDIP packages. The byte-
wide data appears on DQ0-DQ7. The device is de-
signed to be programmed in-system with the standard
system 5.0 Volt V
quired for program or erase operations. The device can
also be programmed or erased in standard EPROM
programmers.
The standard device offers access times of 45, 55, 70,
90, and 120 ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus con-
tention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE) controls.
The device requires only a single 5.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the pro-
gramming and erase operations. Reading data out of
the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This invokes the Embedded Pro-
gram algorithm—an internal algorithm that automati-
cally times the program pulse widths and verifies
proper cell margin.
2
CC
supply. A 12.0 volt V
PP
is not re-
Am29F010
Device erasure occurs by executing the erase com-
mand sequence. This invokes the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is erased
when shipped from the factory.
The hardware data protection measures include a
low V
during power transitions. The hardware sector pro-
tection feature disables both program and erase oper-
ations in any combination of the sectors of memory,
and is implemented using standard EPROM program-
mers.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
h i gh est l eve l s o f qu al i ty, r el i a bi l i t y, a nd c o s t
effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of hot
electron injection.
CC
detector automatically inhibits write operations