TE28F160S570 Intel, TE28F160S570 Datasheet
TE28F160S570
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TE28F160S570 Summary of contents
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... V program/erase lockout during power transitions. These alternatives give designers ultimate control of their code security needs. This family of products is manufactured on Intel industry-standard 56-lead SSOP. In addition, the 16-Mb device is available in the industry-standard 56-lead TSOP package. ...
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... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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... Block Status Register ........................ 19 4.2.4 CFI Query Identification String........... 20 4.2.5 System Interface Information............. 21 4.2.6 Device Geometry Definition ............... 22 4.2.7 Intel-Specific Extended Query Table . 23 4.3 Read Identifier Codes Command ............. 24 4.4 Read Status Register Command.............. 24 4.5 Clear Status Register Command.............. 25 4.6 Block Erase Command ............................ 25 4 ...
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... Added Max values for Erase, Write, and Lock-Bit performance, Section 6.7. Corrected Figure 11, Comments section from “Data = D0H” to “Data = 01H.” Added Table 18 to reflect de-rated read performance specifications. Name of document changed from Word-Wide FlashFile™ Memory Family 28F160S5, 28F320S5. 4 ...
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... Finally, Section 7.0 provides ordering and reference information. 1.1 New Features The 5 Volt FlashFile memory family maintains basic compatibility with Intel’s 28F016SA and 28F016SV. Key enhancements include: Common Flash Interface (CFI) Support Scaleable Command Set (SCS) Support Enhanced Suspend Capabilities They share a compatible status register, basic software commands, and pinout ...
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Individual block locking uses a combination of block lock-bits to lock and unlock blocks. Block lock-bits gate block erase, full chip erase, program and write to buffer operations. Lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits commands) ...
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Table 1. Pin Descriptions Sym Type A –A INPUT ADDRESS INPUTS: Address inputs for read and write operations are internally 0 21 latched during a write cycle x16 mode not used; input buffer is off. 0 ...
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... ighlights pinout changes. Figure 3. 28F320S5 and 28F160S5 SSOP 56-Lead Pinout 2.0 PRINCIPLES OF OPERATION The 5 Volt FlashFile memories include an on-chip Write State Machine (WSM) to manage block erase, program, and lock-bit configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure, ...
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... Block 000000 Byte-Wide (x8) Mode 10 3.0 BUS OPERATION After The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Block information, query information, identifier codes and status ...
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... RESET# signal that resets the system CPU. 3.5 Read Query Operation The read query operation outputs block status, Common Flash Interface (CFI) ID string, system interface, device geometry, and Intel-specific extended query information. 3.6 Read Identifier Codes Operation The read-identifier codes operation outputs the ...
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A[ ]: 16-Mbit 20 32-Mbit 21-1 Word (Subsequent Blocks) Address 0FFFF Block 1 Reserved for Future Implementation 08004 08003 Block 1 Lock Configuration 08002 Reserved for Future Implementation 08000 07FFF Block 0 Reserved for Future Implementation 00004 ...
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Table 2. Bus Operations Mode Notes RP Read 1 Output Disable Standby Reset/Power Down Mode Read Identifier ...
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... Table 3. 5 Volt FlashFile™ Memory (28F160S5, 28F320S5) Command Set Definitions Command Scaleable Bus or Basic Cycles Command Req'd Set (14) Read Array SCS/BCS 1 Read Identifier Codes SCS/BCS Read Query SCS Read Status Register SCS/BCS 2 Clear Status Register SCS/BCS 1 Write to Buffer SCS > ...
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... Commands other than those shown above are reserved for future use and should not be used. 14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set. ...
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... Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI ...
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Table 4. Summary of Query Structure Output as a Function of Device and Mode Device Type/Mode Word Addressing Location x16 device/ 10h x16 mode 11h 12h x16 device/ N/A (1) x8 mode NOTE: 1. The system must drive the lowest ...
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... Refer to Section 4.2.1 and Table 4 for the detailed definition of offset address as a function of device word width and mode The beginning location of a Block Address (i.e., 08000h is the beginning location of block 1 when the block size is 32 Kword). 3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table. 18 (1) ...
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... BLOCK STATUS REGISTER The block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Table 7. Block Status Register Offset Length (bytes) (1) (BA+2)h 01h Block Status Register BSR.0 = Block Lock Status 1 = Locked 0 = Unlocked BSR ...
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... CFI QUERY IDENTIFICATION STRING The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which vendor- specified command set(s) is (are) supported. Table 8. CFI Identification Offset Length (Bytes) 10h 03h Query-Unique ASCII string “ ...
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SYSTEM INTERFACE INFORMATION The following device information can be useful in optimizing system interface software. Table 9. System Interface Information Offset Length (bytes) 1Bh 01h V Logic Supply Minimum Program/Erase Voltage CC bits 7–4 BCD volts bits 3–0 BCD ...
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... DEVICE GEOMETRY DEFINITION This field provides critical details of the flash device geometry. Table 10. Device Geometry Definition Offset Length Description (bytes) 27h 01h Device Size = Number of Bytes 28h 02h Flash Device Interface Description value 0002h 2Ah 02h Maximum Number of Bytes in Write Buffer ...
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... INTEL-SPECIFIC EXTENDED QUERY TABLE Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information. Table 11. Primary-Vendor Specific Extended Query Offset (1) Length (bytes) (P)h 03h Primary Extended Query Table Unique ASCII String “PRI“ ...
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Table 11. Primary-Vendor Specific Extended Query (Continued) Offset Length (bytes) (P+C)h 01h V Logic Supply Optimum Program/Erase voltage CC (highest performance) bits 7–4 bits 3–0 (P+D)h 01h V [Programming] Supply Optimum Program/Erase PP voltage bits 7–4 bits 3–0 (P+E)h ...
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Following a program, block erase, set block lock-bit, or clear block lock-bits command sequence, only SR.7 is valid until the Write State Machine completes or suspends the operation. Device I/O pins DQ and DQ are invalid. When the 0-6 8-15 ...
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... After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM to begin copying the buffer data to the flash memory command other than Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated and status register bits SR.5 and SR.4 will be set to “ ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear ...
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The only other valid commands while programming is suspended are Read Status Register and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. Status register bits SR.2 and SR.7 will automatically ...
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... WSM is busy. configuration 01 ER INT, pulse mode —used to generate a system interrupt pulse when any flash device in an array has completed a block erase or sequence of queued block erases. Helpful for reformatting blocks after file system free space reclamation or ‘cleanup’ ...
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Table 15. Status Register Definition WSMS ESS ECLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block erase suspended 0 = Block erase in progress/completed ...
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... N = 00H to 1FH and for word mode are N = 0000H to 000FH. 2. The device now outputs the status register when read (XSR is no longer available). 3. Write Buffer contents will be programmed at the device start address or destination flash address. 4. Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A address = 0). ...
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Start Write 40H, Address Write Data and Address Read Status Register No Suspend 0 SR.7 = Byte/Word Program 1 Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 ...
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Start Write B0H Read Status Register 0 SR SR.2 = Programming Completed 1 Write FFH Read Data Array No Done Reading Yes Write D0H Write FFH Programming Resumed Read Array Data Figure 8. Program Suspend/Resume Flowchart PRELIMINARY ...
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... Write Confirm D0H Block Address Another Issue Read Block Status Command Erase? No Read Status Register 0 SR Full Status Check if Desired Erase Flash Block(s) Complete Figure 9. Block Erase Flowchart 34 Bus Command Operation Write Erase Block Read Standby Write Erase Block Read Standby ...
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Start Write B0H Read Status Register 0 SR SR.6 = Block Erase Completed 1 Read Program Read or Program? Read Array Program No Data Loop Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data ...
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Start Write 60H, Block/Device Address Write 01H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range ...
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Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range Error 0 1 SR. ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control Intel provides three control inputs to accommodate multiple memory connections ( OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation; b. Data bus contention avoidance. To use these control inputs efficiently, an address decoder should enable CEx# while OE# should be connected to all memory devices and the system’ ...
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... PRELIMINARY NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “ ...
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Capacitance T = +25 ° MHz A Symbol Parameter C Input Capacitance IN C Output Capacitance OUT NOTE: 1. Sampled, not 100% tested. 6.4 DC Characteristics – +85 ...
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DC Characteristics (Continued – +85 C (Extended) and T A Sym Parameter I V Programming and Set CCW CC Lock-Bit Current I V Block Erase or Clear Block CCE CC Lock-Bits Current I ...
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... V 5. Automatic Power Savings (APS) reduces typical I 6. CMOS inputs are either V ± 0 GND ± 0.2 V. TTL inputs are either Sampled, not 100% tested. 8. With V V flash memory writes are inhibited. CC LKO °C to +70 °C (Commercial) A Notes Min Max ...
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Input 1.5 0.0 AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to ...
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AC Characteristics—Read-Only Operations – +85 C (Extended) and T A Versions (4) (All units in ns unless otherwise noted) # Sym Parameter R1 t Read/Write Cycle Time AVAV R2 t Address to ...
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Device Standby Address Selection V IH ADDRESSES ( ( OE# ( WE# ( DATA (D/Q) High Z (DQ0-DQ15 ...
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AC Characteristics—Write Operations – +85 C (Extended) and T A Versions (6) # Sym RP# High Recovery to WE# (CE ) PHWL PHEL Setup ...
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ADDRESSES [ (WE#) [E(W OE# [ WE# (CE #) [W(E ...
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V IH STS ( RP# ( CC1 Figure 18. AC Waveform for Reset Operation Table 18. Reset AC Specifications # Sym Parameter P1 t RP# ...
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Erase, Write, and Lock-Bit Configuration Performance 5 V ± 5 ± 10 Version # Sym W16 Byte/word program time (using write buffer) W16 t Per byte program time (without write buffer) WHQV1 t EHQV1 W16 ...
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... ORDERING INFORMATION Package DT = Extended Temp. 56-Lead SSOP TE = Extended Temp. 56-Lead TSOP Product Line Designator for all Intel Flash products Device Density 160 = 16 Mbit 320 = 32 Mbit Order Code by Density TE28F160S5-70 TE28F160S5-100 DT28F160S5-70 DT28F320S5-90 DT28F160S5-100 DT28F320S5-110 50 Access Speed (ns) Device Type Product Family S = FlashFile™ ...
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... CFI - Common Flash Interface Reference Code Sales Office NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. ...