TE28F160S570 Intel, TE28F160S570 Datasheet - Page 25

• Manufacturer Part Number: TE28F160S570
• Manufacturer: Intel

Specifications of TE28F160S570

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

Following a program, block erase, set block lock-bit,
or clear block lock-bits command sequence, only
SR.7 is valid until the Write State Machine
completes or suspends the operation. Device I/O
pins DQ
operation completes or suspends (SR.7 = 1), all
contents of the status register are valid when read.
The eXtended Status Register (XSR) may be read
to determine Write Buffer availability (see Table 16).
The XSR may be read at any time by writing the
Write to Buffer command. After writing this
command, all subsequent read operations output
data from the XSR, until another valid command is
written. The contents of the XSR are latched on the
falling edge of OE# or CE
in the read cycle. Write to buffer command must be
re-issued to update the XSR latch.
4.5
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to “1”s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 15).
By allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or programming several
bytes/words in sequence) may be performed. The
status register may be polled to determine if an
error occurred during the sequence.
To clear the status register, the Clear Status
Register
independently of the applied V
command is not functional during block erase or
program suspend modes.
4.6
Block Erase is executed one block at a time and
initiated by a two-cycle command. A Block Erase
Setup command is written first, followed by a
Confirm
requires appropriate sequencing and an address
within the block to be erased (erase changes all
block data to FFH). Block preconditioning, erase,
and verify are handled internally by the WSM
(invisible to the system). After the two-cycle block
erase sequence is written, the device automatically
outputs status register data when read (see Figure
9). The CPU can detect block erase completion by
PRELIMINARY
0-6
Clear Status Register
Command
Block Erase Command
command.
command
and DQ
8-15
This
is
X
are invalid. When the
# whichever occurs last
written.
command
PP
voltage. This
It
sequence
functions
analyzing STS in level RY/BY# mode or status
register bit SR.7. Toggle OE#, CE
update the status register.
When the block erase is complete, status register
bit SR.5 should be checked. If a block erase error is
detected, the status register should be cleared
before system software attempts corrective actions.
The CUI remains in read status register mode until
a new command is issued.
This two-step command sequence of set-up
followed by execution ensures that block contents
are not accidentally erased. An invalid Block Erase
command sequence will result in both status
register bits SR.4 and SR.5 being set to “1.” Also,
reliable block erasure can only occur when
V
these voltages, block contents are protected
against erasure. If block erase is attempted while
V
Successful
corresponding block lock-bit be cleared, or WP# =
V
corresponding block lock-bit is set and WP# = V
the block erase will fail and SR.1 and SR.5 will be
set to “1.”
4.7
The Full Chip Erase command followed by a
Confirm command erases all unlocked blocks. After
the Confirm command is written, the device erases
all unlocked blocks from block 0 to block 31 (or 63)
sequentially. Block preconditioning, erase, and
verify are handled internally by the WSM. After the
Full Chip Erase command sequence is written to
the CUI, the device automatically outputs the status
register data when read. The CPU can detect full
chip erase completion by polling the STS pin in
level RY/BY# mode or status register bit SR.7.
When the full chip erase is complete, status register
bit SR.5 should be checked to see if the operation
completed successfully. If an erase error occurred,
the status register should be cleared before issuing
the next command. The CUI remains in read status
register mode until a new command is issued. If an
error is detected while erasing a block during a full
chip erase operation, the WSM skips the remaining
cells in that block and proceeds to erase the next
block. Reading the block valid status code by
issuing the Read Identifier Codes command or
Query command informs the user of which block(s)
failed to erase.
CC
PP
IH
. If block erase is attempted when the
= V
V
CC1/2
PPLK
Full Chip Erase Command
, SR.3 and SR.5 will be set to “1.”
block
and V
PP
erase
= V
28F160S5/28F320S5
PPH
requires
. In the absence of
0
#, or CE
that
1
# to
the
25
IL,