ISP1362BD NXP Semiconductors, ISP1362BD Datasheet - Page 104

• Manufacturer Part Number: ISP1362BD
• Description: USB Interface IC USB OTG CONTROLLER
• Manufacturer: NXP Semiconductors

Specifications of ISP1362BD

• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1362BD,157

NXP Semiconductors
Table 97.
Table 99.
ISP1362_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 0
Symbol
PTDDoneBits
[31:0]
HcATLBlkSize register: bit allocation
HcATLPTDDoneMap register: bit description
14.9.4 HcATLPTDDoneMap register (R: 1Bh)
14.9.5 HcATLPTDSkipMap register (R/W: 1Ch/9Ch)
R/W
15
7
0
-
-
Code (Hex): 54 — read
Code (Hex): D4 — write
Table 98.
This is a 32-bit register. The bit description of the register is given in
the register represents the processing status of a PTD. Bit 0 of the register represents the
first PTD stored in the ATL buffer, bit 1 represents the second PTD stored in the buffer,
and so on. The register is immediately updated after the completion of each ATL PTD
processing. It is cleared when read by the HCD. Bits that are set represent its
corresponding PTDs have been processed by the Host Controller and an ACK token has
been received from the device.
Code (Hex): 1B — read only
This is a 32-bit register, and the bit description is given in
represents the first PTD stored in the ATL buffer, bit 1 represents the second PTD stored
in the buffer, and so on. When the bit is set by the HCD, the corresponding PTD is skipped
and is not processed by the Host Controller. The Host Controller processes the skipped
PTD only if the HCD has reset its corresponding skipped bit to logic 0. Clearing the
corresponding bit in the HcATLPTDSkipMap register when there is no valid data in the
block will cause unpredictable behavior of the Host Controller.
Code (Hex): 1C — read
Code (Hex): 9C — write
Bit
15 to 10
9 to 0
Access
R
R/W
14
6
0
-
-
Value
0000h
HcATLBlkSize register: bit description
Symbol
-
BlockSize[9:0]
R/W
13
Description
0 — The PTD stored in the ATL buffer was not successfully processed by the
Host Controller.
1 — The PTD stored in the ATL buffer was successfully processed by the
Host Controller.
5
0
-
-
reserved
Rev. 05 — 8 May 2007
Description
reserved
The block size of the ATL buffer.
R/W
12
4
0
-
-
BlockSize[7:0]
R/W
11
3
0
-
-
Single-chip USB OTG Controller
R/W
10
2
0
Table
-
-
100. Bit 0 of the register
Table
R/W
R/W
9
0
1
0
BlockSize[9:8]
© NXP B.V. 2007. All rights reserved.
ISP1362
99. Every bit of
103 of 152
R/W
R/W
8
0
0
0