DAC1210LCJ-1 National Semiconductor, DAC1210LCJ-1 Datasheet - Page 13

• Manufacturer Part Number: DAC1210LCJ-1
• Description: DAC 1-CH R-2R 12-Bit 24-Pin CDIP
• Manufacturer: National Semiconductor

Specifications of DAC1210LCJ-1

• Package: 24CDIP
• Resolution: 12 Bit
• Architecture: R-2R
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 1
• Output Type: Current
• Full Scale Error: -0.2 %FSR
• Integral Nonlinearity Error: ±0.05 %FSR
• Maximum Settling Time: 1(Typ) us

Application Hints
Transient response and settling time of the op amp are im-
portant in fast data throughput applications The largest sta-
bility problem is the feedback pole created by the feedback
resistance R
This appears from the op amp output to the (
includes the stray capacitance at this node Addition of a
lead capacitance C
and ringing at the output for a step change in DAC output
current
2 1 1 Zero and Full-Scale Adjustments
For accurate conversions the input offset voltage of the
output amplifier must always be nulled Amplifier offset er-
rors create an overall degradation of DAC linearity
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near 0 V
This is accomplished by shorting out R
back resistor and adjusting the v
the op amp until the output reads zero volts This is done of
course with an applied digital code of all zeros if I
driving the op amp (all ones for I
R
A unique feature of this series of DACs is that the full-scale
or gain error is guaranteed to be negative The gain error
specification is a measure of how close the value of the
Fb
is then removed and the converter is zero adjusted
Fb
and the output capacitance of the DAC
C
in Figure 9 greatly reduces overshoot
(Continued)
OS
OUT2
1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0
nulling potentiometer of
FIGURE 10 Bipolar Output Voltage Configuration
Fb
MSB
) The short around
Input Code
the amplifier feed-
DC
b
as possible
LSB
) input and
OUT1
is
b
V
V
13
REF
REF
b
V
2
a
b
REF
1 LSB
V
V
b
internal feedback resistor R
resistors A negative gain error indicates that R
er resistance value than it should be To adjust this gain
error some resistance must always be added in series with
R
the worst-case gain error for these devices
2 2 Bipolar Output Voltage from a Fixed Reference
The addition of a second op amp to the unipolar circuit can
generate a bipolar output voltage from a fixed reference
voltage This in effect gives sign significance to the MSB of
the digital input word to allow two quadrant multiplication of
the reference voltage The polarity of the reference can also
be reversed to realize full 4-quadrant multiplication This cir-
cuit is shown in Figure 10
This configuration features several improvements over ex-
isting circuits for a bipolar output shown with other multiply-
ing DACs Only the offset voltage of amplifier 1 affects the
linearity of the DAC The offset voltage error of the second
op amp (although a constant output error) has no effect on
linearity In addition this configuration offers a non-interac-
tive positive and negative full-scale calibration procedure
0
REF
b
REF
Fb
1 LSB
2
1 LSB
The 50
Ideal V
OUT
b
l
V
l
potentiometer shown is sufficient to adjust
V
REF
b
2
REF
a
a
b
l
V
l
l
1 LSB
V
V
REF
a
l
0
REF
REF
a
1 LSB
l
1 LSB
l
2
V
for 0
1 LSB
OUT
Fb
s
e
e
matches the R-2R ladder
D
V
l
V
2048
REF
s
REF
4095
l
D
b
2048
2048
Fb
TL H 5690-16
is a small-