DAC1210LCJ-1 National Semiconductor, DAC1210LCJ-1 Datasheet - Page 6

• Manufacturer Part Number: DAC1210LCJ-1
• Description: DAC 1-CH R-2R 12-Bit 24-Pin CDIP
• Manufacturer: National Semiconductor

Specifications of DAC1210LCJ-1

• Package: 24CDIP
• Resolution: 12 Bit
• Architecture: R-2R
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 1
• Output Type: Current
• Full Scale Error: -0.2 %FSR
• Integral Nonlinearity Error: ±0.05 %FSR
• Maximum Settling Time: 1(Typ) us

Application Hints
1 0 DIGITAL INTERFACE
These DACs are designed to provide all of the necessary
digital input circuitry to permit a direct interface to a wide
variety of microprocessor systems The timing and logic lev-
el convention of the input control signals allow the DACs to
be treated as a typical memory device or I O peripheral with
no external logic required in most systems Essentially
these DACs can be mapped as a two-byte stack in memory
(or I O space) to receive their 12 bits of input data in two
successive 8-bit data writing sequences The DAC1230 se-
ries is intended for use in systems with an 8-bit data bus
The DAC1208 series provides all 12 digital input lines which
can be externally configured to be controlled from an 8-bit
bus or can be driven directly from a 16-bit data bus
FIGURE 1 DAC1208 DAC1209 DAC1210 Functional Diagram
FIGURE 2 DAC1230 DAC1231 DAC1232 Functional Diagram
6
All of the digital inputs to these DACs contain a unique
threshold regulator circuit to maintain TTL voltage level
compatibility independent of the applied V
Any input can also be driven from higher voltage CMOS
logic levels in non-microprocessor based systems To pre-
vent damage to the chip from static discharge all unused
digital inputs should be tied to V
shooting aid if any digital input is inadvertently left floating
the DAC will interpret the pin as a logic ‘‘1’’
Double buffered digital inputs allow the DAC to internally
format the 12-bit word used to set the current switching R-
2R ladder network (see section 2 0) from two 8-bit data
write cycles Figures 1 and 2 show the internal data regis-
ters and their controlling logic circuitry The timing diagrams
for updating the DAC output are shown in sections 1 1 1 2
and 1 3 for three possible control modes The method used
depends strictly upon the particular application
CC
or ground As a trouble-
CC
to the DAC
TL H 5690 – 6