SAB-C165-LM Infineon Technologies, SAB-C165-LM Datasheet - Page 11

• Manufacturer Part Number: SAB-C165-LM
• Description: MCU 16-Bit C166 CISC/RISC ROMLess 5V 100-Pin MQFP
• Manufacturer: Infineon Technologies

Specifications of SAB-C165-LM

• Package: 100MQFP
• Family Name: C166
• Maximum Speed: 20 MHz
• Ram Size: 2 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Program Memory Type: ROMLess
• Number Of Programmable I/os: 77
• Interface Type: ASC/SSC
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 5

Table 2
Symbol Pin Nr
P4
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
RD
WR/
WRL
READY 35
ALE
EA
Data Sheet
TQFP
23
24
25
26
29
30
31
32
33
34
36
37
Pin Definitions and Functions (cont’d)
38
Pin Nr
MQFP
25
26
27
28
31
32
33
34
35
36
37
39
Input
Outp.
IO
O
O
O
O
O
O
O
O
O
O
I
O
I
Function
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits.
For a pin configured as input, the output driver is put
into high-impedance state. Port 4 can be used to
output the segment address lines:
A16 Least Significant Segment Address Line
A17 Segment Address Line
A18 Segment Address Line
A19 Segment Address Line
A20 Segment Address Line
A21 Segment Address Line
A22 Segment Address Line
A23 Most Significant Segment Address Line
External Memory Read Strobe. RD is activated for
every external instruction or data read access.
External Memory Write Strobe. In WR-mode this pin
is activated for every external data write access. In
WRL-mode this pin is activated for low byte data
write accesses on a 16-bit bus, and for every data
write access on an 8-bit bus. See WRCFG in register
SYSCON for mode selection.
Ready Input. When the Ready function is enabled, a
high level at this pin during an external memory
access will force the insertion of memory cycle
waitstates until the pin returns to a low level.
An internal pullup device holds this pin high when
nothing is driving it.
Address Latch Enable Output. Can be used for
latching the address into external memory or an
address latch in the multiplexed bus modes.
External Access Enable pin. A low level at this pin
during and after Reset forces the C165 to begin
instruction execution out of external memory. A high
level forces execution out of the internal program
memory.
“ROMless” versions must have this pin tied to ‘0’.
7
V2.0, 2000-12
C165