GS88036BGT-200 GSI TECHNOLOGY, GS88036BGT-200 Datasheet - Page 5

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GS88036BGT-200

Manufacturer Part Number
GS88036BGT-200
Description
SRAM Chip Sync Quad 2.5V/3.3V 9M-Bit 256K x 36 6.5ns/3ns 100-Pin TQFP Tray
Manufacturer
GSI TECHNOLOGY
Datasheet

Specifications of GS88036BGT-200

Package
100TQFP
Timing Type
Synchronous
Density
9 Mb
Data Rate Architecture
SDR
Typical Operating Supply Voltage
2.5|3.3 V
Address Bus Width
18 Bit
Number Of I/o Lines
36 Bit
Number Of Ports
4
Number Of Words
256K
TQFP Pin Description
Rev: 1.05 11/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
B
ADSP, ADSC
A
Symbol
, B
A
E
V
ADV
DQ
DQ
DQ
DQ
LBO
V
V
BW
GW
NC
0
B,
CK
1
ZZ
FT
E
DDQ
A
G
, A
, E
DD
SS
B
2
A
B
C
D
C
1
3
, B
D
Type
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
5/24
Address Strobe (Processor, Cache Controller); active low
Address field LSBs and Address Counter preset Inputs
Byte Write Enable for DQ
Burst address counter advance enable; active low
Global Write Enable—Writes all bytes; active low
Byte Write—Writes all enabled bytes; active low
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Sleep Mode control; active high
Clock Input Signal; active high
Output driver power supply
Data Input and Output pin
Output Enable; active low
Chip Enable; active high
Chip Enable; active low
I/O and Core Ground
Core power supply
Address Inputs
Description
No Connect
GS88018/32/36BT-333/300/250/200/150
A
, DQ
B
Data I/Os; active low
© 2002, GSI Technology

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